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2020 IEEE International Test Conference (ITC)最新文献

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A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices 一种提高集成无源器件质量和可靠性的深度学习筛选方法
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325221
Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, C. Tsai, Hao Chen, Min-Jer Wang
{"title":"A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices","authors":"Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, C. Tsai, Hao Chen, Min-Jer Wang","doi":"10.1109/ITC44778.2020.9325221","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325221","url":null,"abstract":"Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the cost of replacing failed IPDs is much higher than the cost of manufacturing them, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automated Assertion Generation from Natural Language Specifications 从自然语言规范自动生成断言
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325264
S. Frederiksen, John J. Aromando, M. Hsiao
{"title":"Automated Assertion Generation from Natural Language Specifications","authors":"S. Frederiksen, John J. Aromando, M. Hsiao","doi":"10.1109/ITC44778.2020.9325264","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325264","url":null,"abstract":"We explore contemporary natural language processing (NLP) techniques for converting NL specifications found in design documents directly to an temporal logic-like intermediate representation (IR). Generally, attempts to use NLP for assertion generation have relied on restrictive sentence formats and grammars as well as being difficult to handle new sentence formats. We tackle these issues by first implementing a system that uses commonsense mappings to process input sentences into a normalized form. Then we use frame semantics to convert the normalized sentences into an IR based on the information and context contained in the Frames. Through this we are able to handle a large number of sentences from real datasheets allowing for complex formats using temporal conditions, property statements, and compound statements; all order agnostic. Our system can also be easy extended by modifying an external, rather than internal, commonsense knowledge-base to handle new sentence formats without requiring code changes or intimate knowledge of the algorithms used.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Avionics Simulation Environment 航电仿真环境
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325215
Hüseyin Sagirkaya, Gökhan Durgun
{"title":"Avionics Simulation Environment","authors":"Hüseyin Sagirkaya, Gökhan Durgun","doi":"10.1109/ITC44778.2020.9325215","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325215","url":null,"abstract":"Avionics simulation environment provides validation and verification of the avionics and helps to test the system evaluating the integration before the aircraft ground and flight tests. In this paper, software and hardware solutions in the avionics test environment are defined. A new software designed for simulating the avionics and data buses is used in the test environment.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic Fault Diagnosis of Hidden Delay Defects 隐性延迟缺陷的逻辑故障诊断
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325234
S. Holst, M. Kampmann, Alexander Sprenger, Jan Dennis Reimer, S. Hellebrand, H. Wunderlich, Xiaoqing Weng
{"title":"Logic Fault Diagnosis of Hidden Delay Defects","authors":"S. Holst, M. Kampmann, Alexander Sprenger, Jan Dennis Reimer, S. Hellebrand, H. Wunderlich, Xiaoqing Weng","doi":"10.1109/ITC44778.2020.9325234","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325234","url":null,"abstract":"Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122796658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors 基于机器学习的速度监视器微控制器性能预测
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325253
R. Cantoro, M. Huch, T. Kilian, R. Martone, Ulf Schlichtmann, Giovanni Squillero
{"title":"Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors","authors":"R. Cantoro, M. Huch, T. Kilian, R. Martone, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/ITC44778.2020.9325253","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325253","url":null,"abstract":"During the manufacturing process, electronic devices are thoroughly tested for defects. However, testing for well-known fault models, such as stuck-at and transition delay, may not be sufficient for an effective performance screening. In modern devices, Design-for-Testability features embedded at design time can allow the tester to apply stimuli and measure different critical parameters. We propose to use some of these structures, namely the speed monitors, to predict the maximum operating speed, and screen out under-performing devices. We design a complete methodology, from the extraction of robust labels, through a machine-learning algorithm, down to a post-processing step, able to meet the quality standards imposed by industry. Experimental results using real production data demonstrate the feasibility of the approach.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128774109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Test and Diagnosis Solution for Functional Safety 功能安全测试与诊断解决方案
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325275
M. Casarsa, Gurgen Harutunyan, Y. Zorian
{"title":"Test and Diagnosis Solution for Functional Safety","authors":"M. Casarsa, Gurgen Harutunyan, Y. Zorian","doi":"10.1109/ITC44778.2020.9325275","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325275","url":null,"abstract":"This paper discusses the automotive requirements of ISO 26262 standard and its implication on conventional test and diagnosis flows. It presents a safety-oriented manufacturing test and diagnosis solution meeting automotive system-on-chip (SoC) requirements. The implementation details, automotive features and experimental results are described showing the effectiveness of the proposed solution.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117120547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In 晶圆级应力:实现无封装老化的汽车微控制器零缺陷质量
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325213
Chen He, Y. Yu
{"title":"Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In","authors":"Chen He, Y. Yu","doi":"10.1109/ITC44778.2020.9325213","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325213","url":null,"abstract":"Automotive microcontrollers demand extremely high reliability requirements. Burn-In (BI) stress to screen out early life failures caused by latent defects has become a quality requirement for automotive semiconductors. However, as feature size continues to scale down, performing BI stress on packaged parts has started to run into challenges including increased risks of thermal runaway and overstress, together with continuously increased cost and cycle time. In this paper, we present a new wafer level stress methodology consisting of enhanced High Voltage Stress Test (eHVST), Wafer Level Burn-In (WLBI), and enhanced Advanced Outlier Limit (eAOL) screens, which can achieve Zero Defect quality for automotive microcontrollers without package BI. It has been successfully implemented in production for NXP S32K1 automotive microcontrollers with benchmark DPPB (Defective Parts Per Billion) level of quality from over 20 million parts shipped in last several years.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"88 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126313117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Test Challenges of Intel IA Cores Intel IA核心的测试挑战
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325265
Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, X. Lin
{"title":"Test Challenges of Intel IA Cores","authors":"Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, X. Lin","doi":"10.1109/ITC44778.2020.9325265","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325265","url":null,"abstract":"This paper presents the structural testing challenges for Intel’s high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel’s IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126463336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introduction to Quantum Computation Reliability 量子计算可靠性概论
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325277
M. Thornton
{"title":"Introduction to Quantum Computation Reliability","authors":"M. Thornton","doi":"10.1109/ITC44778.2020.9325277","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325277","url":null,"abstract":"An overview of the quantum computing paradigm with a focus on reliability is provided in a tutorial form intended for practitioners and researchers in the test and reliability community. It is assumed that readers have little prior knowledge of quantum informatics. An introductory description of the mathematical models of a qubit and quantum information processing operations and projective measurement is presented as background. Discussions of quantum error sources and associated fault models are included using the concepts and notation explained in the background section. Topics related to the decoherence problem are also included. The concept of a logical qubit and how quantum error detection and correction can be applied to enhance reliability of quantum computations is formulated using the notions of classical fault models and error detection and correction techniques. The general concept of quantum error detection and correction as applied to enhancing quantum computational reliability is discussed including an example of one of the first such methods originally introduced in 1995.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125193506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fail Memory Configuration Set for RA Estimation RA估计的Fail Memory Configuration Set
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325273
Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong
{"title":"Fail Memory Configuration Set for RA Estimation","authors":"Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong","doi":"10.1109/ITC44778.2020.9325273","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325273","url":null,"abstract":"Since the redundancy analysis (RA) has been introduced for memory yield, many RA researches have been conducted. However, objective comparisons of them are difficult by the absence of real memory models with realistic fault distributions. This paper presents a fail memory configuration set for RA estimation, called as ITC’2020 RA Benchmarks. It enables objective estimations of RAs with respect to effectiveness and efficiency. The fail memory configuration set includes memory models which have various redundancy structures and a fault generation algorithm with fault distribution which can be criteria for objective comparisons of RA. Simulations for estimations and comparisons of RA researches including BIRA are progressed utilizing the fail memory configuration set.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128022538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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