Test Challenges of Intel IA Cores

Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, X. Lin
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Abstract

This paper presents the structural testing challenges for Intel’s high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel’s IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.
Intel IA核心的测试挑战
本文介绍了英特尔高性能IA核的结构测试挑战以及为克服这些挑战而开发的新颖ATPG解决方案。英特尔的IA core采用了一种设计结构,对行业标准的测试设计(DFT)工具提出了独特的测试挑战。首先,在采用两相时钟方案时,普遍使用锁存器和触发器。其次,基于结构的模式重用功能时钟网络,因此保持了与功能测试相似的性能和功耗配置文件。这种设计特性引入了独特的自动测试模式生成(ATPG)挑战。本文将介绍为处理这些独特设计而开发的设计规则检查(drc)的创新增强。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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