Test Challenges of Intel IA Cores

Abstract

This paper presents the structural testing challenges for Intel’s high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel’s IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.