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ITC 2020 Paper Selection Process ITC 2020论文选择流程
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/itc44778.2020.9325211
{"title":"ITC 2020 Paper Selection Process","authors":"","doi":"10.1109/itc44778.2020.9325211","DOIUrl":"https://doi.org/10.1109/itc44778.2020.9325211","url":null,"abstract":"","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131492717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New Perspectives on Core In-field Path Delay Test 磁芯场内路径延迟测试新进展
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325260
R. Cantoro, Dario Foti, Sandro Sartoni, M. Reorda, L. Anghel, M. Portolan
{"title":"New Perspectives on Core In-field Path Delay Test","authors":"R. Cantoro, Dario Foti, Sandro Sartoni, M. Reorda, L. Anghel, M. Portolan","doi":"10.1109/ITC44778.2020.9325260","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325260","url":null,"abstract":"Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains, widely supported by commercial tools. However, functional testing may be a desirable choice in this context because it allows to catch faults at-speed with no hardware overhead and it can be used both for endof-manufacturing tests and for in-field test. The purpose of this article is to compare the results that can be achieved with both approaches. This work is based on an open-source RISC-V-based processor core as benchmark device. Gathered results show that there is no correlation between stuck-at and path delay fault coverage, and provide guidelines for developing more effective functional test.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131043518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing 数字和混合信号电路测试签名分析仪的统一设计方法
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325274
V. Geurkov, L. Kirischian
{"title":"A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing","authors":"V. Geurkov, L. Kirischian","doi":"10.1109/ITC44778.2020.9325274","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325274","url":null,"abstract":"We present a simple unified approach to designing algebraic/arithmetic signature analyzers. The design technique is valid for an arbitrary number system. The proposed devices have low hardware complexity and low aliasing rate. The technique can also be used in error-control coding and cryptography.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IJTAG Through a Two-Pin Chip Interface IJTAG通过双引脚芯片接口
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325232
M. Baby, Bernd Büttner, P. Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, J. Cote, G. Danialy, Martin Keim, Lori Schramm
{"title":"IJTAG Through a Two-Pin Chip Interface","authors":"M. Baby, Bernd Büttner, P. Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, J. Cote, G. Danialy, Martin Keim, Lori Schramm","doi":"10.1109/ITC44778.2020.9325232","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325232","url":null,"abstract":"IEEE 1687 (IJTAG) provides significant value to the DFT engineer and efficiency in the DFT flow. However, IJTAG requires 4 or 5 pins to drive an IEEE 1149.1 compliant TAP controller. Many of our designs have fewer than 4 pins total, prohibiting the usage of IJTAG. In this paper we describe a solution that drives an embedded TAP controller from a chip interface that consists of only 2 ports, a clock port and a bidirectional data port. The embedded TAP then drives the IJTAG network as usual, providing us all the benefits of IJTAG. To enable this, we needed to expand the used EDA tool’s IJTAG support in the direction of IEEE P1687.1. Experiences from the implementation of this solution in a productive chip show significant productivity gains.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Learning A Wafer Feature With One Training Sample 用一个训练样本学习一个晶圆特征
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325254
Y. Zeng, Li-C. Wang, Chuanhe Jay Shan, N. Sumikawa
{"title":"Learning A Wafer Feature With One Training Sample","authors":"Y. Zeng, Li-C. Wang, Chuanhe Jay Shan, N. Sumikawa","doi":"10.1109/ITC44778.2020.9325254","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325254","url":null,"abstract":"In this work, we consider learning a wafer plot recognizer where only one training sample is available. We introduce an approach called Manifestation Learning to enable the learning. The underlying technology utilizes the Variational AutoEncoder (VAE) approach to construct a so-called Manifestation Space. The training sample is projected into this space and the recognition is achieved through a pre-trained model in the space. Using wafer probe test data from an automotive product line, this paper explains the learning approach, its feasibility and limitation.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling Novel Non-JTAG IEEE 1687-Like Architectures 新型非jtag IEEE 1687类架构建模
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325248
M. Laisne, A. Crouch, M. Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, B. G. V. Treuren, J. Rearick
{"title":"Modeling Novel Non-JTAG IEEE 1687-Like Architectures","authors":"M. Laisne, A. Crouch, M. Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, B. G. V. Treuren, J. Rearick","doi":"10.1109/ITC44778.2020.9325248","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325248","url":null,"abstract":"Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. These ICs can’t afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design often results in having an instrument buried deep inside a device, the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies.In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, an In-System TAP, IEEE 1149.7like interface, and a security block.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115792428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors 高性能计算处理器安全故障率的测量研究
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325239
R. Bramley, Yanxiang Huang, Guangshan Duan, N. Saxena, Paul Racunas
{"title":"On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors","authors":"R. Bramley, Yanxiang Huang, Guangshan Duan, N. Saxena, Paul Racunas","doi":"10.1109/ITC44778.2020.9325239","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325239","url":null,"abstract":"Accurate determination of the safe-fault failure rate of complex digital designs is an exascale problem. We present a novel measurement methodology and results which could have a profound impact on the performance and availability for GPUs in safety critical systems. We extend our analysis with a methodology for in-the-field verification.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction 采用低延迟小电压调节器和轻量电流预测的主动电源噪声缓解
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325257
Jun Chen, M. Hashimoto
{"title":"Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction","authors":"Jun Chen, M. Hashimoto","doi":"10.1109/ITC44778.2020.9325257","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325257","url":null,"abstract":"Power supply noise induces extra timing delay or even malfunctions in modern power-demanding VLSI chips. Traditional reactive noise mitigation is often too late to suppress emergent supply noise due to the long latency of voltage boosting. This paper proposes a proactive method for mitigating emergent supply noises and avoiding unexpected failures in power-hungry VLSI designs with two contributions. First, a major-minor voltage regulator (MMVR) structure, which enables quick and widerange voltage scaling with small ripples, is proposed. Second, a lightweight current predictor consisting of a six-layer decision tree regressor achieves over 0.98 correlation for 50-cycle-ahead prediction in 25 RISC-V benchmark programs. Experimental results with a multi-core RISC-V design show that the proposed method mitigates the supply noise within 30 mV while the noise exceeds 70 mV with the conventional reactive mitigation. Also, the average supply voltage is compensated during the powerdemanding operation.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130325430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling Accuracy of Wideband Power Amplifiers with Memory effects via Measurements 基于测量的具有记忆效应的宽带功率放大器建模精度
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325245
Wei Gao, Tao Jing
{"title":"Modeling Accuracy of Wideband Power Amplifiers with Memory effects via Measurements","authors":"Wei Gao, Tao Jing","doi":"10.1109/ITC44778.2020.9325245","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325245","url":null,"abstract":"In this paper, an accurate modeling approach to wideband Wi-Fi power amplifiers (PA) with memory effects is presented. Modeling accuracy is improved by interpolating the measured data from a low sampling rate of 40 MHz to high data rates with different interpolation factors based on the propagation delay of the actual PA. A memory polynomial (MP) model of the PA is able to characterize both nonlinear properties and memory effects of the actual PA; especially for wide bandwidth Wi-Fi OFDM signal transmission. With this improved MP model of the PA, another similar memory polynomial model for the predistorter (PD) is developed to linearize wideband WiFi PAs.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114214129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks 未来IEEE P1687.1 IJTAG网络的多级访问保护
2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325276
David Brauchler, Jennifer Dworak
{"title":"Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks","authors":"David Brauchler, Jennifer Dworak","doi":"10.1109/ITC44778.2020.9325276","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325276","url":null,"abstract":"Embedded instruments are responsible for aiding in a wide range of tasks engineers must perform on integrated circuits (ICs), including testing, debugging, and analysis. The IEEE 1687 IJTAG standard provides efficient access to these instruments without specifying proper measures to establish access control to sensitive data on the ICs. Previously, the impact of this exposure was generally limited to local attackers obtaining proprietary information from a device to which they have physical access. However, newer endeavors such as IEEE P1687.1 aim to extend IJTAG access to other serial ports, broadening the attack surface to additional local and remote attackers alike. In order to protect these components from local and remote attackers, we describe a lightweight and low-cost protocol to authenticate users that offers solutions to access control, key distribution, and insecure secrets stored on-chip.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127018193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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