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2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)最新文献

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Dark current noise and noise gain in quantum-well infrared photodetectors 量子阱红外光电探测器中的暗电流噪声和噪声增益
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940112
A. D. B. Maia, B. P. Figueroa, A. T. Bezerra, R. Kawabata, M. Pires, P. Souza
{"title":"Dark current noise and noise gain in quantum-well infrared photodetectors","authors":"A. D. B. Maia, B. P. Figueroa, A. T. Bezerra, R. Kawabata, M. Pires, P. Souza","doi":"10.1109/SBMICRO.2014.6940112","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940112","url":null,"abstract":"Dark current noise in InGaAs/InAlAs quantum well infrared photodetectors has been investigated as a function of temperature and bias voltage. From the current noise dependence on these parameters the noise gain has been determined.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126154729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs 高温对非对称自级联码SOI nmosfet模拟参数的影响
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940135
L. d'Oliveira, D. Flandre, M. Pavanello, M. de Souza
{"title":"Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs","authors":"L. d'Oliveira, D. Flandre, M. Pavanello, M. de Souza","doi":"10.1109/SBMICRO.2014.6940135","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940135","url":null,"abstract":"This paper presents an analysis on the high temperature operation of Silicon-on-Insulator (SOI) nMOSFETs in Asymmetric Self-Cascode (A-SC) configuration. For this analysis, experimental results in the range of 300K to 500K of A-SC structures with different channel lengths for both the drain side transistor (MD) and source side transistor (MS) are used. The effect of varying channel length under high temperatures on the A-SC association is evaluated using as figure of merit important analog parameters, such as the intrinsic voltage gain and transconductance over drain current ratio.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"51 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs 采用OCTO布局方式提高了mosfet的辐射硬度和更高的重建前rad条件
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940133
Leonardo Navarenho de Souza Fino, M. A. Guazzelli da Silveira, C. Renaux, D. Flandre, Salvador Pinillos Gimenez
{"title":"Boosting the radiation hardness and higher reestablishing pre-rad conditions by using OCTO layout style for MOSFETs","authors":"Leonardo Navarenho de Souza Fino, M. A. Guazzelli da Silveira, C. Renaux, D. Flandre, Salvador Pinillos Gimenez","doi":"10.1109/SBMICRO.2014.6940133","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940133","url":null,"abstract":"This manuscript has the objective to perform an experimental comparative analysis of the total ionizing dose influence in the Silicon-On-Insulator Metal-Oxide-Semiconductor Field Effect Transistor implemented with the octagonal gate shape (OCTO) and the standard one (rectangular gate shape) counterpart, after a X-ray radiation exposure. The back-gate bias technique is applied in these devices to reestablish the threshold voltage and subthreshold slope that were degraded by the ionizing radiation effects. Since the octagonal layout style maintains a better electrical performance after radiation, a smaller back-gate bias to recover the pre-rad operation is required in comparison to the conventional counterpart. This is mainly because the parasitic transistors in the bird's beak region are practically deactivated by the particular octagonal gate geometry.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115107429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A prospective on education of new generations of devices in the FDSOI and FinFET technologies: From the technological process to the circuit design specifications FDSOI和FinFET技术中新一代器件的教育展望:从工艺过程到电路设计规范
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940081
O. Bonnaud, L. Fesquet
{"title":"A prospective on education of new generations of devices in the FDSOI and FinFET technologies: From the technological process to the circuit design specifications","authors":"O. Bonnaud, L. Fesquet","doi":"10.1109/SBMICRO.2014.6940081","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940081","url":null,"abstract":"The upcoming of FDSOI and FinFET technologies at nanoscale enlarges the gap between education and industry. Indeed, no university is able to provide access to such technologies before post-graduation. In addition, the situation is similar when looking at the integrated circuit design. The incredible degrees of freedom offered by the CAD tools to designers and the need to integrate more constraints makes really challenging the design of complex integrated circuits. The universities are facing really difficult issues on pedagogical point of view: designing and fabricating integrated circuits with no real experience in the advanced technologies and the design techniques. In this context, this paper investigates what should be the content of curricula of Masters or engineers diploma in order to efficiently prepare the students to work as well in this industry as in the research laboratories. Several suggestions will be provided.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121992204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of high temperature on substrate effect of UTBB SOI nMOSFETs 高温对UTBB SOI nmosfet衬底效应的影响
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940132
V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino
{"title":"Influence of high temperature on substrate effect of UTBB SOI nMOSFETs","authors":"V. Itocazu, V. Sonnenberg, E. Simoen, C. Claeys, J. Martino","doi":"10.1109/SBMICRO.2014.6940132","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940132","url":null,"abstract":"An analysis of the temperature influence on the substrate effect of short channel Ultra Thin Body and BOX (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation is presented. This study was done from room temperature up to 200°C. The theoretical model was applied and the results are in agreement with experimental and simulation data. The data shows a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop over the gate and buried oxides. The maximum difference between VGB with and without GP decreases for high temperature.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors n型和p型SOI无结纳米线晶体管的有效迁移率分析
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940108
R. Doria, R. Trevisoli, M. de Souza, M. Pavanello
{"title":"Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors","authors":"R. Doria, R. Trevisoli, M. de Souza, M. Pavanello","doi":"10.1109/SBMICRO.2014.6940108","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940108","url":null,"abstract":"This paper reports the behavior of the effective mobility of n- and p-type SOI Trigate Junctionless Nanowire Transistors with different doping concentrations and channel widths down to 20 nm-wide devices. It is shown that the mobility of extremely narrow devices can overcome the bulk silicon mobility independently of the device type. The increase in the maximum mobility observed in narrow devices seems to be more pronounced for heavier doped devices.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124130945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application 提出一种仅使用三个光刻步骤的全耗尽SOI nMOSFET的工艺设计方法，用于教育应用
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940124
R. Rangel, J. Martino
{"title":"Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application","authors":"R. Rangel, J. Martino","doi":"10.1109/SBMICRO.2014.6940124","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940124","url":null,"abstract":"This paper presents, for the first time in Latin America, a simple process design methodology of Fully Depleted (FD) Silicon-On-Insulator (SOI) nMOSFET for educational application in microelectronic. A simple SOI process flow with only three photolithograph steps is proposed, thanks to the fact of using the buried oxide (intrinsic to SOI wafers) as field region, with avoid the necessity of using the contact mask. The FD SOI nMOSFETs and a complete chip test was fabricated and characterized electrically at University of Sao Paulo, resulting in good performance of SOI devices with transistor channel length from 50μm down to 0.5μm due to the thin channel silicon film as is shown in this paper. In spite of this simple SOI nMOSFET technology was developed mainly for educational proposes, it can be useful also for basic research study.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115917398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
TeO2-ZnO thin films with gold nanoparticles as passivating materials for power devices applications 含金纳米颗粒的TeO2-ZnO薄膜在功率器件中的钝化应用
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940090
L. Bontempo, S. G. dos Santos Filho, L. Kassab
{"title":"TeO2-ZnO thin films with gold nanoparticles as passivating materials for power devices applications","authors":"L. Bontempo, S. G. dos Santos Filho, L. Kassab","doi":"10.1109/SBMICRO.2014.6940090","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940090","url":null,"abstract":"TeO2-ZnO thin films with gold nanoparticles have been grown by magnetron co-sputtering process at the RF power around 50W followed by annealing at 325°C during 10 and 20h. The electrical properties of these films were analyzed from Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics and were correlated to the size and distribution of nanoparticles obtained with aid of transmission electron microscopy. It was inferred, from C-V and I-V curves, a significant leakage current in the inversion region for all samples. Also, the leakage current increased and the flatband voltage shift decreased when the thickness of the TeO2-ZnO films, annealed at 325°C for 20h, was decreased from 500 to 10nm. These results showed that the leakage current of the films can be controlled by varying the thickness, which makes them potential passivating materials for power devices applications.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132160711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Study of pH sensors based on TiO2 nanotubes 基于TiO2纳米管的pH传感器研究
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940087
G. Z. Monteiro, P. Marques, I. Pereyra, K. F. Albertin
{"title":"Study of pH sensors based on TiO2 nanotubes","authors":"G. Z. Monteiro, P. Marques, I. Pereyra, K. F. Albertin","doi":"10.1109/SBMICRO.2014.6940087","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940087","url":null,"abstract":"TiO2 nanotube arrays obtained by Ti foil anodization are tested as pH electrodes, showing performance close to standard glass electrodes. The TiO2 nanotube arrays were obtained by Ti foil anodization in a NH4F organic solution with 20, 40 and 60 V and different anodization times. The obtained nanotubes samples were characterized by Scanning Electron Microscopy (SEM). Electrode modified by TiO2 nanotubes were characterized in pH buffer solution (pH of 4.0, 7.0 and 10.0) and the obtained results show that electrode modified by NTs obtained with anodization voltage of 40 V with 45 minutes presents an almost linear response close to Nernst equation (59 mV/pH).","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of the semi-insulating properties of Al2O3 and AlHfO3.5 for power devices 功率器件用Al2O3和AlHfO3.5半绝缘性能的表征
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2014-10-30 DOI: 10.1109/SBMICRO.2014.6940119
B. Alandia, D. R. Huanca, V. Christiano, S. G. dos Santos Filho
{"title":"Characterization of the semi-insulating properties of Al2O3 and AlHfO3.5 for power devices","authors":"B. Alandia, D. R. Huanca, V. Christiano, S. G. dos Santos Filho","doi":"10.1109/SBMICRO.2014.6940119","DOIUrl":"https://doi.org/10.1109/SBMICRO.2014.6940119","url":null,"abstract":"Physical and electrical characterization of alumina and hafnium aluminates gate dielectrics were carried out to investigate their semi-insulating characteristics as passivating layer for power devices. The deposited films were annealed in pure nitrogen to simulate the thermal budget during a conventional CMOS processing. C-V measurements were performed having as a result a high-frequency behavior of the flat band voltage (VFB) being increased from about -0.8V for Al2O3 to values greater than or equal to zero for AlHfO3.5. On the other hand, the leakage phenomenon was modeled with a simplified electrical model using a leakage admittance YC whose influence was predominant at the accumulation region. Using X-ray reflectometry (XRR), the average thickness obtained was 15.5nm and a leakage process was inferred to occur for AlHfO3.5 due to the observed phase separation and crystallization that occurs after annealing in pure N2.","PeriodicalId":244987,"journal":{"name":"2014 29th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122499969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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