Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Abstract

An analysis of the temperature influence on the substrate effect of short channel Ultra Thin Body and BOX (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation is presented. This study was done from room temperature up to 200°C. The theoretical model was applied and the results are in agreement with experimental and simulation data. The data shows a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop over the gate and buried oxides. The maximum difference between VGB with and without GP decreases for high temperature.