Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application

Abstract

This paper presents, for the first time in Latin America, a simple process design methodology of Fully Depleted (FD) Silicon-On-Insulator (SOI) nMOSFET for educational application in microelectronic. A simple SOI process flow with only three photolithograph steps is proposed, thanks to the fact of using the buried oxide (intrinsic to SOI wafers) as field region, with avoid the necessity of using the contact mask. The FD SOI nMOSFETs and a complete chip test was fabricated and characterized electrically at University of Sao Paulo, resulting in good performance of SOI devices with transistor channel length from 50μm down to 0.5μm due to the thin channel silicon film as is shown in this paper. In spite of this simple SOI nMOSFET technology was developed mainly for educational proposes, it can be useful also for basic research study.