2007 International Symposium on System-on-Chip最新文献_第3页

A New LMMSE Receiver Architecture With Dynamic Filter Length Optimisation 一种新的LMMSE接收机结构与动态滤波器长度优化

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427439

M. Tennant, A. Erdogan, T. Arslan, J. Thompson

引用次数: 1

Rendezvous-based MoC for untimed TLM 非定时TLM的基于会合点的MoC

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427449

R. Jindal, L. Maillet-Contoz

引用次数: 0

3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus 3gb /s，多点总线双向数据单端自适应均衡

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427445

H. Fredriksson, C. Svensson

引用次数: 2

Control and datapath decoupling in the design of a NoC switch: area, power and performance implications NoC开关设计中的控制和数据路径解耦:面积、功率和性能影响

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427438

S. Medardoni, D. Bertozzi, L. Benini, E. Macii

引用次数: 9

Configurable Hardware/Software Support for Single Processor Real-Time Kernels 单处理器实时内核的可配置硬件/软件支持

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427426

S. Nordstrom, L. Asplund

{"title":"Configurable Hardware/Software Support for Single Processor Real-Time Kernels","authors":"S. Nordstrom, L. Asplund","doi":"10.1109/ISSOC.2007.4427426","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427426","url":null,"abstract":"Today's software based real-time operating systems (RTOS) have the ability to be configured in order to decrease memory footprint, important when the RTOS is used in resource restricted embedded environments. When the kernel is implemented in hardware, not only memory footprint is motivation for configuration for minimization, the number of logic cells occupied in the PPGA has to be considered as well. We have modified existing hardware support, the real-time unit (RTU) for increased configurability. The modified RTU was compared regarding configuration and footprint with a corresponding system based on the commercial software RTOS MicroC/OS-ll. Four different configuration settings were compared and the results show that the RTU memory footprint was 24% to 38% of the size of the MicroC/OS-II footprint. In FPGA area, the smallest configuration of the RTU occupied only 50% of the logic cells used by the largest configuration. Configurability of an RTOS with hardware support, like the RTU, decreases project cost since it is more likely to be able to use a low cost FPGA when adjusting implemented functionality to only include what is required by the application.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116343369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates 使用便携式预合成模板管理异构核心中的可重构资源

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427446

M. Santambrogio, M. Giani, S. Memik

{"title":"Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates","authors":"M. Santambrogio, M. Giani, S. Memik","doi":"10.1109/ISSOC.2007.4427446","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427446","url":null,"abstract":"In this paper we consider multi-FPGAs, reconfiguration and system description portability as the processes of specifying and modeling a complete system before it is partitioned and committed to a style/flow of implementation. In the case of a high performance computing cluster employing FPGAs, the reconfigurable elements need to be dynamically re-allocated and reconfigured based on the prevailing workload at a given instance. We particularly target fast configuration and task migration in high performance computing systems, such as server farms. This paper presents a design flow, based in resource sharing across configurations on the reconfigurable devices, which can manage the resource allocation and reconfiguration quickly when resources need to be migrated between different applications. The resources shared across configuration are defined using an isomorphic-driven partitioning approach. This technique detects recurrent structures and produces a partitioned specification in which the identified clusters are instances of repeating templates in the original graph used to describe the input application. Two algorithms for regularity extraction were implemented. The performances of the algorithms were compared with regard to the size and number of regular structures identified by the two approaches, as well as the lime taken to perform their task.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The Bulk Built In Current Sensor Approach for Single Event Transient Detection 单事件瞬态检测的批量内置电流传感器方法

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427422

G. Wirth, C. Fayomi

引用次数: 20

MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip 一种降低片上多处理器系统温度梯度的任务迁移算法

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427441

S. Carta, Fabio Mereu, A. Acquaviva, G. Micheli

引用次数: 8

Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC 多处理器SoC上分布任务图映射算法的最优子集映射及收敛性评价

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427433

Heikki Orsila, E. Salminen, Marko Hännikäinen, T. Hämäläinen

{"title":"Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC","authors":"Heikki Orsila, E. Salminen, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/ISSOC.2007.4427433","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427433","url":null,"abstract":"Mapping an application on multiprocessor system-on-chip (MPSoC) is a crucial step in architecture exploration. The problem is to minimize optimization effort and application execution time. Applications are modeled as static acyclic task graphs which are mapped to an MPSoC. The analysis is based on extensive simulations with 300 node graphs from the standard graph set. We present a new algorithm, optimal subset mapping (OSM), that rapidly evaluates task distribution mapping space, and then compare it to simulated annealing (SA) and group migration (GM) algorithms. OSM was developed to make architecture exploration faster. Efficiency of OSM is 5.0 times and 2.4 times than that of GM and SA, respectively, when efficiency is measured as the application speedup divided by the number of iterations needed for optimization. This saves 81% and 62% in wall clock optimization time, respectively. However, this is a tradeoff because OSM reaches 96% and 89% application speedup compared to GM and SA. Results show that OSM and GM have opposite convergence behavior and SA comes between these two.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Is Your Low Power Design Switched On? 你的低功耗设计开启了吗?

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427451

M. Croft, Stephen Bailey

{"title":"Is Your Low Power Design Switched On?","authors":"M. Croft, Stephen Bailey","doi":"10.1109/ISSOC.2007.4427451","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427451","url":null,"abstract":"Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation-dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellcra's Unified Power Format standard for low power design intent and using UPF for verification.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124161251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3