你的低功耗设计开启了吗?

M. Croft, Stephen Bailey
{"title":"你的低功耗设计开启了吗?","authors":"M. Croft, Stephen Bailey","doi":"10.1109/ISSOC.2007.4427451","DOIUrl":null,"url":null,"abstract":"Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation-dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellcra's Unified Power Format standard for low power design intent and using UPF for verification.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Is Your Low Power Design Switched On?\",\"authors\":\"M. Croft, Stephen Bailey\",\"doi\":\"10.1109/ISSOC.2007.4427451\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation-dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellcra's Unified Power Format standard for low power design intent and using UPF for verification.\",\"PeriodicalId\":244119,\"journal\":{\"name\":\"2007 International Symposium on System-on-Chip\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on System-on-Chip\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2007.4427451\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on System-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2007.4427451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

功率是大多数电子系统设计的关键驱动因素。管理系统电源以延长电池寿命并减少电力消耗和热量产生是开发移动电话、便携式导航系统和计算服务器等许多类型系统的关键考虑因素。新的设计技术包括时钟门控、功率门控、多电压和动态电压和频率缩放,以降低动态和静态能耗。低功耗电子系统的设计带来了新的设计和验证挑战。今天的片上系统由接近或超过100万个门的大型IP块组成。如何在不需要修改和耗时的重新验证IP的黄金RTL代码的情况下应用系统低功耗设计意图?如何在设计过程的早期验证功率门控、保留和隔离的功能影响,因为它更便宜,更容易解决问题?能否在合成之前验证依赖于实现的低功耗设计功能,如准确的保留、保存和恢复协议?在本次演讲中,我们将讨论Accellcra的统一电源格式标准,用于低功耗设计意图和使用UPF进行验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Is Your Low Power Design Switched On?
Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation-dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellcra's Unified Power Format standard for low power design intent and using UPF for verification.
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