2007 International Symposium on System-on-Chip最新文献

A New Look at Reversible Logic Implementation of Decimal Adder 十进制加法器可逆逻辑实现新探

2007 International Symposium on System-on-Chip Pub Date : 2007-11-20 DOI: 10.1109/ISSOC.2007.4427442

Rekha K. James, T. Shahana, K. Poulose Jacob, S. Sasi

引用次数: 25

A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor Architecture 基于可重构多处理器体系结构的认知无线电系统级设计方法

2007 International Symposium on System-on-Chip Pub Date : 2007-11-20 DOI: 10.1109/ISSOC.2007.4427419

Qiwei Zhang, A. Kokkeler, G. Smit

引用次数: 3

Implementing the conjugate gradient algorithm on multi-core systems 共轭梯度算法在多核系统上的实现

2007 International Symposium on System-on-Chip Pub Date : 2007-11-20 DOI: 10.1109/ISSOC.2007.4427436

Wouter Wiggers, V. Bakker, A. Kokkeler, G. Smit

引用次数: 34

Sensor Network-On-Chip 传感器Network-On-Chip

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427447

G. Varatkar, S. Narayanan, Naresh R Shanbhag, Douglas L. Jones

引用次数: 26

Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding 运行时计划的MPEG-4视频解码硬件加速

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427425

J. Boutellier, P. Jääskeläinen, O. Silvén

{"title":"Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding","authors":"J. Boutellier, P. Jääskeläinen, O. Silvén","doi":"10.1109/ISSOC.2007.4427425","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427425","url":null,"abstract":"In this paper we present a hardware-accelerated system-on-chip implementation of an MPEG-4 simple profile video decoder with a novel hardware accelerator interfacing methodology. The system consists of a general purpose master processor and several slave hardware accelerators. The communication between the master processor and the hardware accelerators is performed without interrupts by using piecewise-static run-time scheduling. After the data content of each macroblock has been discovered, the master processor computes a short static schedule for the accelerators. This removes the need for the accelerators to interrupt the master processor when the assigned task is finished. Therefore, context save overheads in the master processor are avoided and energy efficiency improves. The accelerators execute functions that perform block-level decoding operations (IDC, inverse quantization etc.), which have deterministic execution times and can be scheduled statically. The task scheduling algorithm executed by the master processor is able to take into account the costs and restrictions of a shared memory with limited access capabilities and marks memory accesses separately to the schedule. The possible heterogeneity of the processing units is also taken care of. Tests show that the proposed scheme is feasible and can be used as an alternative to traditional synchronization methods.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128444773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation 一种基于特征的光流处理器架构，具有单运动矢量/周期生成功能

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427444

Kazuhide Fujita, Kiyoto Ito, T. Shibata

引用次数: 6

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology NoCRay图形加速器:MP-SoC片上网络设计方法的案例研究

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427429

S. Tota, M. Casu, P. Ros, M. R. Roch, M. Zamboni

引用次数: 2

A Configuration Locking Technique to Reduce the Configuration Overhead of Run-Time Reconfigurable Devices 一种减少运行时可重构设备配置开销的配置锁定技术

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427423

Yang Qu, J. Soininen, J. Nurmi

引用次数: 0

Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication 采用线性分段总线和通信处理器来降低同步片上通信的能耗

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427432

Kris Heyrman, A. Papanikolaou, F. Catthoor, P. Veelaert, W. Philips

{"title":"Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication","authors":"Kris Heyrman, A. Papanikolaou, F. Catthoor, P. Veelaert, W. Philips","doi":"10.1109/ISSOC.2007.4427432","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427432","url":null,"abstract":"The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we save energy by consequently switching off unused bus sections on a cycle-by-cycle basis. The communication processor is a paradigm for the control of such a bus by means of software. Synchronous communication takes place within the tiles of a SoC in the deep sub-micron technology domain. We explore design alternatives for a linear software-controlled sectioned bus while building the hardware model of a single-instruction-issue processor, and run, in simulation, a media benchmark on it. We determine the energy cost of controlling this bus, compare it with the energy gain obtained from the sectioning, and find it favorable. The control cost is only 5% of the bus transport energy, leaving us with a gain by segmentation of 81%. We demonstrate the feasibility of the control of a low-power synchronous communication system by the processor. Starting out from this case study at the low-end to medium range of network complexity, we consider the implications of growing complexity that will arise from using multiple sectioned buses on multiple-issue computers (VLIWs). We find that control of linear bus topologies of medium-level complexity is now well understood. Further work is needed at the high-end of non-linear topologies.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"18 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reduce SOC Energy Consumption through Processor ISA Extension 通过处理器ISA扩展降低SOC能耗

2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427427

S. Leibson

引用次数: 3