Sensor Network-On-Chip

Abstract

In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed to recover the performance of the system in the presence of errors especially timing errors. We apply this framework to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Simulations in IBM's 130 nm CMOS process technology demonstrate up to 30% power savings compared to the conventional architecture for a detection probability of PD = 0.5.