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Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture 采用时域计算结构的混合信号焦平面图像处理器
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427428
Kiyoto Ito, T. Shibata
{"title":"Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture","authors":"Kiyoto Ito, T. Shibata","doi":"10.1109/ISSOC.2007.4427428","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427428","url":null,"abstract":"A mixed-signal focal-plane image processor for realtime spatiotemporal convolution has been developed based on the time-domain computation technique. Pixel information is represented as a pulse width, and all computations are carried out using simple digital logic gates and a binary counter equipped in each pixel processing element. As a result, both the compactness of analog and programmability of digital have been achieved. The concept was verified by a prototype chip fabricated in a 0.18-mum CMOS technology, demonstrating over 78,000 convolutions/s with 1.0V supply.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128488016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power Management and Clock Generator for a Novel Passive UWB Tag 一种新型无源超宽带标签的电源管理和时钟发生器
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427448
M. Nejad, H. Tenhunen, Lirong Zheng
{"title":"Power Management and Clock Generator for a Novel Passive UWB Tag","authors":"M. Nejad, H. Tenhunen, Lirong Zheng","doi":"10.1109/ISSOC.2007.4427448","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427448","url":null,"abstract":"In this paper we present a power management and a clock generator for a novel passive UWB tag. It can be used in many applications such as radio frequency Identification (RFID), and ubiquitous wireless sensing. As same as conventional RFID, the tag captures the power from the incoming RF signal, converts to DC and stores it in a relatively big capacitor. A voltage sensor and a regulator provide stable voltage for the whole circuitry during operation mode. A clock circuitry generates a low jitter and low skew clock for ultra wideband transmitter to transmit data. In such passive system the power consumption of each block should be as low as possible. On the other hand, performance degradation across process, voltage, and temperature variation (PVT) is another problematic challenge in low power and low cost circuit implementation. In this work, the power management unit including of an RF power scavenging, a voltage sensor, a low drop out regulator and a clock generator are designed and their performance across PVT variation are analyzed. The module is designed and is fabricated in CMOS 0.18 mum technology.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134028471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC 基于10gb /s锁相环的SOC片间通信反序列化器的CMOS IC设计与Verilog-A建模
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427420
M. Assaad, D. Cumming
{"title":"CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC","authors":"M. Assaad, D. Cumming","doi":"10.1109/ISSOC.2007.4427420","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427420","url":null,"abstract":"The results of design and simulation of a novel architecture for a 10 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the serializer/deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 mum CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132683151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Heuristics for Scenario Creation to Enable General Loop Transformations 场景创建的启发式方法以启用一般循环转换
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427430
M. Palkovic, H. Corporaal, F. Catthoor
{"title":"Heuristics for Scenario Creation to Enable General Loop Transformations","authors":"M. Palkovic, H. Corporaal, F. Catthoor","doi":"10.1109/ISSOC.2007.4427430","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427430","url":null,"abstract":"Embedded system applications can have quite complex control flow graphs (CFGs). Often their control flow prohibits design time optimizations, like advanced global loop transformations. To solve this problem, and enable far more global optimizations, we could consider paths of the CFG in isolation. However coding all paths separately would cause a tremendous code copying. In practice we have to trade-off the extra optimization opportunities vs. the code size. To make this trade-off, in this paper we use so-called system scenarios. These scenarios bundle similar control paths, while still allowing sufficient optimizations. The problem treated in this paper is: what are the right scenarios; i.e., which paths should be grouped together. For complex CFGs the number of possible scenarios (ways of grouping CFG paths) is huge; it grows exponentially with the number of CFG paths. Therefore heuristics are needed to quickly discover reasonable groupings. The main contribution of this paper is that we propose and evaluate three of these heuristics on both synthetic benchmarks and on a real-life application.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126067946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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