{"title":"采用时域计算结构的混合信号焦平面图像处理器","authors":"Kiyoto Ito, T. Shibata","doi":"10.1109/ISSOC.2007.4427428","DOIUrl":null,"url":null,"abstract":"A mixed-signal focal-plane image processor for realtime spatiotemporal convolution has been developed based on the time-domain computation technique. Pixel information is represented as a pulse width, and all computations are carried out using simple digital logic gates and a binary counter equipped in each pixel processing element. As a result, both the compactness of analog and programmability of digital have been achieved. The concept was verified by a prototype chip fabricated in a 0.18-mum CMOS technology, demonstrating over 78,000 convolutions/s with 1.0V supply.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture\",\"authors\":\"Kiyoto Ito, T. Shibata\",\"doi\":\"10.1109/ISSOC.2007.4427428\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A mixed-signal focal-plane image processor for realtime spatiotemporal convolution has been developed based on the time-domain computation technique. Pixel information is represented as a pulse width, and all computations are carried out using simple digital logic gates and a binary counter equipped in each pixel processing element. As a result, both the compactness of analog and programmability of digital have been achieved. The concept was verified by a prototype chip fabricated in a 0.18-mum CMOS technology, demonstrating over 78,000 convolutions/s with 1.0V supply.\",\"PeriodicalId\":244119,\"journal\":{\"name\":\"2007 International Symposium on System-on-Chip\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on System-on-Chip\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2007.4427428\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on System-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2007.4427428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
基于时域计算技术,研制了一种用于实时时空卷积的混合信号焦平面图像处理器。像素信息表示为脉冲宽度,所有计算都使用简单的数字逻辑门和每个像素处理单元中配备的二进制计数器进行。从而实现了模拟的紧凑性和数字的可编程性。该概念通过采用0.18 μ m CMOS技术制造的原型芯片进行验证,在1.0V电源下显示超过78,000个卷积/s。
A mixed-signal focal-plane image processor for realtime spatiotemporal convolution has been developed based on the time-domain computation technique. Pixel information is represented as a pulse width, and all computations are carried out using simple digital logic gates and a binary counter equipped in each pixel processing element. As a result, both the compactness of analog and programmability of digital have been achieved. The concept was verified by a prototype chip fabricated in a 0.18-mum CMOS technology, demonstrating over 78,000 convolutions/s with 1.0V supply.