十进制加法器可逆逻辑实现新探

Rekha K. James, T. Shahana, K. Poulose Jacob, S. Sasi
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引用次数: 25

摘要

当考虑最小能量耗散计算时,可逆性起着基本的作用。近年来,可逆逻辑在低功耗CMOS、量子计算和纳米技术等领域得到了广泛的应用,成为功率优化的重要途径之一。本研究提出了一种可逆逻辑的二进制编码十进制(BCD)加法器。与现有的BCD加法器可逆逻辑实现相比,该设计减少了门和垃圾输出的数量。因此,这种设计产生了一个减少面积和延迟的实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A New Look at Reversible Logic Implementation of Decimal Adder
Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gates and garbage outputs compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay.
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