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Managing Concurrency by Supporting Object-oriented Programming with Hybrid Data-driven Control-flow Processor 混合数据驱动控制流处理器支持面向对象编程的并发管理
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427421
Raimo Mäkelä, O. Vainio
{"title":"Managing Concurrency by Supporting Object-oriented Programming with Hybrid Data-driven Control-flow Processor","authors":"Raimo Mäkelä, O. Vainio","doi":"10.1109/ISSOC.2007.4427421","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427421","url":null,"abstract":"More and more processors can be fabricated on a single chip today. But management of this increasing parallelism is still in a research phase. This paper introduces the idea of the hybrid data-driven control-flow processor. The hybrid processor has support for object-oriented programming methods to help programmers to manage parallelism in the network of the hybrid processors. All programs, including the operating system, can be divided to several objects and thus spread over the network. This way everything is executed truly concurrently in the network of the hybrid processors.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127174763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-Optimal Circuit Design 能量优化电路设计
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427450
S. Hanson, Bo Zhai, D. Blaauw, D. Sylvester
{"title":"Energy-Optimal Circuit Design","authors":"S. Hanson, Bo Zhai, D. Blaauw, D. Sylvester","doi":"10.1109/ISSOC.2007.4427450","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427450","url":null,"abstract":"Energy efficiency is an emerging metric for the quality of integrated circuit designs. Applications ranging from wireless sensor networks to RFID tags to embedded microprocessors require extremely low power consumption to maintain good battery life. We advocate the use of aggressively scaled supply voltages in such applications to maximize energy efficiency. This paper reviews our recent progress in mapping out the low energy design space including the presence of an energy-optimal supply voltage, and also touches on complications arising from variability at low supply voltages. We conclude with a survey of open research directions in the ultra-low voltage design space.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122287672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Development of Complex SoC Devices Require New Design Technologies 复杂SoC器件的发展需要新的设计技术
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427435
G. Schreiner
{"title":"Development of Complex SoC Devices Require New Design Technologies","authors":"G. Schreiner","doi":"10.1109/ISSOC.2007.4427435","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427435","url":null,"abstract":"Developers of System on Chips devices are facing a constantly increasing demand for more complex and powerful products that need to be developed in very short time frames. These challenges can be mastered only by the use of a development environment that allows the developer to work on a high level of abstraction with the possibility to integrate existing IP.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Algorithm for Fast Statistical Timing Analysis 快速统计时序分析算法
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427424
J. Salzmann, F. Sill, D. Timmermann
{"title":"Algorithm for Fast Statistical Timing Analysis","authors":"J. Salzmann, F. Sill, D. Timmermann","doi":"10.1109/ISSOC.2007.4427424","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427424","url":null,"abstract":"Problems of parameter variations are a main topic in current research and will gain importance in future technology generations due to the continuing scaling. Therefore, it requires appropriate timing analysis which is traditionally done with corner-case simulations. These are quite conservative and pessimistic approaches. In contrast, new statistical static timing analysis (SSTA) algorithms offer a more accurate prediction of the timing behavior of circuit designs. Further, correlations between various parameters and devices can be observed. Unfortunately, the SSTA algorithms mostly require high computational effort and accurate library characterization. This paper proposes an approach for a fast statistical static timing analysis (F-SSTA) with moderate requirements on computation time and library characterization. The approach considers the analysis of gates with multiple inputs. The simulation results show an average error of 5% compared to Monte-Carlo simulations but a significant speed improvement of around 20 times compared to a highly accurate SSTA algorithm.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"152 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114062257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Novel Emulation Technique that Preserves Circuit Structure and Timing 一种保留电路结构和时序的新型仿真技术
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427437
Leos Kafka, M. Danek, O. Novák
{"title":"A Novel Emulation Technique that Preserves Circuit Structure and Timing","authors":"Leos Kafka, M. Danek, O. Novák","doi":"10.1109/ISSOC.2007.4427437","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427437","url":null,"abstract":"This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114284171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems 多asip soc -或如何为无线和多媒体系统设计超低功耗架构
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427452
G. Goossens
{"title":"Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems","authors":"G. Goossens","doi":"10.1109/ISSOC.2007.4427452","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427452","url":null,"abstract":"In the next years, multi-processor systems-on-chip (MPSoC) are expected to become the platform of choice for new feature-rich devices in high-volume markets like wireless telecom and portable multi-media. With increasing chip densities and an ever growing quest for both more functionality and longer battery autonomy, low energy consumption becomes of the essence in the design of these SoCs. The International Roadmap for Semiconductors (ITRS) shows that the power budget (allowable consumption in Watts) for chips for battery-powered hand-held systems will remain constant in the next decade. The reduction of technology geometries will not automatically result in significant power savings because of the growing importance of static (or leakage) power. Therefore, new architectural methodologies are indispensable to meet the power challenges of SoCs. In this presentation we will review architectural strategies for the design of ultra-low power SoCs. Drawing from experience in power-sensitive market segments like hearing instruments, we contend that MPSoC architectures must be heterogeneous to meet the ultra-low power requirements of next-generation telecom and multi-media systems. Rather than replicating identical processor cores and let them communicate via a general-purpose on-chip network, we propose that each processor core as well as the communication network is optimised for the application. This provides for an optimal balance of arithmetic units, and both task-level, data-level, and instruction-level parallelism, resulting in lowest energy consumption. Multi-core SoCs based on application-specific instruction-set processors (ASIPs) thus allow to push the power envelope to the next level.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128341634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA Prototype of the REALJava Co-Processor REALJava协处理器的FPGA原型
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427434
T. Säntti, Joonas Tyystjärvi, J. Plosila
{"title":"FPGA Prototype of the REALJava Co-Processor","authors":"T. Säntti, Joonas Tyystjärvi, J. Plosila","doi":"10.1109/ISSOC.2007.4427434","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427434","url":null,"abstract":"This paper presents the FPGA prototype of the REALJava co-processor. The virtual machine architecture is described along with the modifications required in the FPGA environment. The FPGA prototype is relevant, as it allows a realistic throughput between the CPU and the co-processor and provides the whole system with a more realistic CPU performance in respect to embedded environments. Our co-processor is designed in a highly modular fashion, especially separating the communication from the actual core. This modularity of the design makes the co-processor more reusable and allows system level scalability. This work is a part of a project focusing on design of an advanced Java co-processor for Java intensive SoC applications.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132738968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mapping streaming applications on a reconfigurable MPSoC platform at run-time 运行时在可重构的MPSoC平台上映射流应用程序
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427443
P. Hölzenspies, G. Smit, J. Kuper
{"title":"Mapping streaming applications on a reconfigurable MPSoC platform at run-time","authors":"P. Hölzenspies, G. Smit, J. Kuper","doi":"10.1109/ISSOC.2007.4427443","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427443","url":null,"abstract":"In this paper we present a method for mapping streaming applications, with real-time requirements, onto a reconfigurable MPSoC. In this method, the performance of the hardware architecture (the reconfigurable Processing Element, the Network Interface and the Network-on-Chip) is integrated in the performance models of the applications. In this way the performance of the mapped application can be determined at runtime. A predictable NoC (guaranteed bandwidth and bounded latency), a predictable Network Interface and a predictable Processing Element are key requirements for our approach.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation 基于K-means算法的实时学习处理器及其种子自动生成
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427431
Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, T. Shibata
{"title":"A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation","authors":"Hirotsugu Shikano, Kiyoto Ito, Kazuhide Fujita, T. Shibata","doi":"10.1109/ISSOC.2007.4427431","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427431","url":null,"abstract":"A full-custom learning processor architecture has been developed based on the K-means algorithm aiming at realtime clustering applications. In order to accelerate the convergence and improve the quality of solutions, an automatic initial seeds generation function has been implemented in the architecture. The concept has been verified by the measurement of the proof-of-concept chip designed and fabricated in a 0.18-mum 5-metal CMOS technology. A full custom chip was also designed using the same technology and sent to fabrication and its operation was confirmed by simulation.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127423821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection 智能摄像机和嵌入式可重构计算:运动检测的案例研究
2007 International Symposium on System-on-Chip Pub Date : 2007-11-01 DOI: 10.1109/ISSOC.2007.4427440
C. Mucci, Luca Vanzolini, A. Deledda, F. Campi, G. Gaillat
{"title":"Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection","authors":"C. Mucci, Luca Vanzolini, A. Deledda, F. Campi, G. Gaillat","doi":"10.1109/ISSOC.2007.4427440","DOIUrl":"https://doi.org/10.1109/ISSOC.2007.4427440","url":null,"abstract":"Image processing for intelligent cameras like those used in video surveillance applications implies computational demanding algorithms activated in function of non predictable events, such as the content of the image or user requests. For such applications, hardwired acceleration must be restricted to a minimum subset of kernels, due to the increasing NREs when application update become necessary. Embedded reconfigurable processors, coupling in the same computing engine a general-purpose embedded processor and field-programmable fabrics, provide an appealing trade-off point between pure software and dedicated hardware acceleration. As a case-study, this paper presents the implementation of a set of image processing operators utilized for motion detection on the DREAM adaptive DSP. With respect to pure software solutions, the proposed implementation achieves a performance improvement of 2-3 orders of magnitude, while retaining the same degree of programmability and the same economical perspectives from the end-user point of view of processor-based approaches.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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