Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems

G. Goossens
{"title":"Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems","authors":"G. Goossens","doi":"10.1109/ISSOC.2007.4427452","DOIUrl":null,"url":null,"abstract":"In the next years, multi-processor systems-on-chip (MPSoC) are expected to become the platform of choice for new feature-rich devices in high-volume markets like wireless telecom and portable multi-media. With increasing chip densities and an ever growing quest for both more functionality and longer battery autonomy, low energy consumption becomes of the essence in the design of these SoCs. The International Roadmap for Semiconductors (ITRS) shows that the power budget (allowable consumption in Watts) for chips for battery-powered hand-held systems will remain constant in the next decade. The reduction of technology geometries will not automatically result in significant power savings because of the growing importance of static (or leakage) power. Therefore, new architectural methodologies are indispensable to meet the power challenges of SoCs. In this presentation we will review architectural strategies for the design of ultra-low power SoCs. Drawing from experience in power-sensitive market segments like hearing instruments, we contend that MPSoC architectures must be heterogeneous to meet the ultra-low power requirements of next-generation telecom and multi-media systems. Rather than replicating identical processor cores and let them communicate via a general-purpose on-chip network, we propose that each processor core as well as the communication network is optimised for the application. This provides for an optimal balance of arithmetic units, and both task-level, data-level, and instruction-level parallelism, resulting in lowest energy consumption. Multi-core SoCs based on application-specific instruction-set processors (ASIPs) thus allow to push the power envelope to the next level.","PeriodicalId":244119,"journal":{"name":"2007 International Symposium on System-on-Chip","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on System-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2007.4427452","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

In the next years, multi-processor systems-on-chip (MPSoC) are expected to become the platform of choice for new feature-rich devices in high-volume markets like wireless telecom and portable multi-media. With increasing chip densities and an ever growing quest for both more functionality and longer battery autonomy, low energy consumption becomes of the essence in the design of these SoCs. The International Roadmap for Semiconductors (ITRS) shows that the power budget (allowable consumption in Watts) for chips for battery-powered hand-held systems will remain constant in the next decade. The reduction of technology geometries will not automatically result in significant power savings because of the growing importance of static (or leakage) power. Therefore, new architectural methodologies are indispensable to meet the power challenges of SoCs. In this presentation we will review architectural strategies for the design of ultra-low power SoCs. Drawing from experience in power-sensitive market segments like hearing instruments, we contend that MPSoC architectures must be heterogeneous to meet the ultra-low power requirements of next-generation telecom and multi-media systems. Rather than replicating identical processor cores and let them communicate via a general-purpose on-chip network, we propose that each processor core as well as the communication network is optimised for the application. This provides for an optimal balance of arithmetic units, and both task-level, data-level, and instruction-level parallelism, resulting in lowest energy consumption. Multi-core SoCs based on application-specific instruction-set processors (ASIPs) thus allow to push the power envelope to the next level.
多asip soc -或如何为无线和多媒体系统设计超低功耗架构
未来几年,多处理器片上系统(MPSoC)有望成为无线电信和便携式多媒体等大容量市场中功能丰富的新设备的首选平台。随着芯片密度的增加以及对更多功能和更长的电池自主性的不断追求,低能耗成为这些soc设计的本质。国际半导体路线图(ITRS)显示,用于电池供电的手持系统的芯片的功率预算(以瓦特为单位的允许消耗)将在未来十年保持不变。由于静态(或泄漏)功率日益重要,技术几何形状的减少不会自动带来显著的功耗节省。因此,新的体系结构方法对于满足soc的性能挑战是必不可少的。在本演讲中,我们将回顾超低功耗soc设计的架构策略。根据听力仪器等功率敏感市场的经验,我们认为MPSoC架构必须是异构的,以满足下一代电信和多媒体系统的超低功耗要求。与其复制相同的处理器核心并让它们通过通用的片上网络进行通信,我们建议每个处理器核心以及通信网络都针对应用进行优化。这提供了算术单元以及任务级、数据级和指令级并行性的最佳平衡,从而实现了最低的能耗。因此,基于特定应用指令集处理器(asip)的多核soc可以将功率包络提升到一个新的水平。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信