ESSCIRC '92: Eighteenth European Solid-State Circuits conference最新文献

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Bridge-to-Frequency Converter for Smart Thermal Flow-Sensor 智能热流量传感器的桥频转换器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468136
Gert J. A. van Dijk, J. H. Huijsing
{"title":"Bridge-to-Frequency Converter for Smart Thermal Flow-Sensor","authors":"Gert J. A. van Dijk, J. H. Huijsing","doi":"10.1109/ESSCIRC.1992.5468136","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468136","url":null,"abstract":"A fully integrated bridge-to-frequency converter is presented as signal-conditioning circuitry for a one-chip smart thermal flow sensor. The converter reads out four separate bridges by means of a multiplexer to realize high sensitivity and directional flow measurement over the full range of 360°. Multiplexer control and output signal are microprocessor compatible. The relative measurement cancels all linear errors. The centre frequency is 10kHz. The sensitivity is 1Hz/(¿V/V). A bridge-offset of 10mV/V is allowed. The linearity error is 0.1%. The supply voltage is 5V.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122234213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Versatile Low Power Oversampled A/D Converter 一种多功能低功耗过采样A/D转换器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468420
O. Nys, E. Dijkstra
{"title":"A Versatile Low Power Oversampled A/D Converter","authors":"O. Nys, E. Dijkstra","doi":"10.1109/ESSCIRC.1992.5468420","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468420","url":null,"abstract":"This paper presents a versatile low power oversampled A/D converter that can be either configured as a sigma delta converter or an incremental converter. The latter refers to oversampled instrumentation converters that cancel offset and 1/f noise. Versatility is achieved by keeping the design completely modular and programmable. Indeed, the implemented converter has been built with a number of identical slices, each consisting of an analog modulator and a companion digital accumulator. Programmable options are: sigma delta or incremental mode, selection of modulator order between 1 and 4, choice of oversampling factor between 2**3 and 2**18, and a comb filter order setting between 1 and 5. The proposed architecture not only leads to simpler structures. It also permits a rapid tailoring of area-optimized A/D converters to given ASIC specifications. In incremental mode, a 16 bits resolution is achieved for DC input values with an integral non-linearity error of ±20 ¿V. Offset and even order harmonics are cancelled to non-observable levels. The power consumption is, in this mode, 20¿A on a supply of ±2 V.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fabrication and Performance of Digital and Analogue Poly-Si TFT Circuits on Glass 玻璃上数字与模拟多晶硅TFT电路的制作与性能
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468208
C. Reita, S. Fluxman, A. Butler, A. J. Lowe, M. Izzard, P. Migliorato, H.G. Yang
{"title":"Fabrication and Performance of Digital and Analogue Poly-Si TFT Circuits on Glass","authors":"C. Reita, S. Fluxman, A. Butler, A. J. Lowe, M. Izzard, P. Migliorato, H.G. Yang","doi":"10.1109/ESSCIRC.1992.5468208","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468208","url":null,"abstract":"Digital and analogue circuits based on polysilicon thin film transistors (poly-Si TFTs) have been designed and fabricated on glass by a low temperature (≪650 C) process. CMOS shift registers and logic circuitry for integrated drivers for AMLCDs and various types of operational amplifier have been fabricated and tested.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115170911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Stable 4th-Order Delta-Sigma Modulator with an FIR predictor 带FIR预测器的稳定四阶δ - σ调制器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468428
Toshiyuki Okanoto, Y. Maruyama, A. Yukawa
{"title":"A Stable 4th-Order Delta-Sigma Modulator with an FIR predictor","authors":"Toshiyuki Okanoto, Y. Maruyama, A. Yukawa","doi":"10.1109/ESSCIRC.1992.5468428","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468428","url":null,"abstract":"A novel approach for a stable high-order delta-sigma modulator is presented. The modulator provides 16 bit resolution at 20kHz bandwidth using 4th-order noise shaping structure at an oversampling ratio of 64. The modulation loop is completely stabilized by an FIR prediction technique. The architecture inherently has less sensitivity to component mismatch. The total hardware is much the same as the noise shaping integrators.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128403890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS Low Distortion Fully Differential Power Amplifier With Double Nested Miller Compensation 一种双嵌套米勒补偿的CMOS低失真全差分功率放大器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468254
S. Pernici, G. Nicollini, R. Castello
{"title":"A CMOS Low Distortion Fully Differential Power Amplifier With Double Nested Miller Compensation","authors":"S. Pernici, G. Nicollini, R. Castello","doi":"10.1109/ESSCIRC.1992.5468254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468254","url":null,"abstract":"A four stages fully-differential amplifier that uses a double nested Miller compensated structure to lower harmonic distortion is presented. With a single 5V supply power dissipation is 10mW and THD is ¿83dB for a 6Vpp differential output signal at 10kHz and a load of 50¿. With 8¿ load and 10kHz, 4Vpp output signal, THD is ¿68dB. The chip area is 1000mils2 in a 1.5¿ n-well CMOS technology.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Design of a Second Order CMOS Sigma-Delta A/D Converter with a 150 MHz Clock Rate 时钟频率为150 MHz的二阶CMOS Sigma-Delta a /D转换器的设计
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468421
B. Hallgren
{"title":"Design of a Second Order CMOS Sigma-Delta A/D Converter with a 150 MHz Clock Rate","authors":"B. Hallgren","doi":"10.1109/ESSCIRC.1992.5468421","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468421","url":null,"abstract":"A continuous time filter current switching sigma delta converter operating at a frequency of 150 MHz has been developed in 2 ¿m CMOS technology. The design of the main components of the converter is described including a very high speed comparator, an integrator and a one bit D/A-converter. Measurements show a 10 bit dynamic range with 9 bit resolution at an oversampling rate of 128.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analog Phase Measuring Circuit for Digital CMOS-ICS 数字CMOS-ICS的模拟相位测量电路
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468148
A. Rothermel, F. Dell'ova
{"title":"Analog Phase Measuring Circuit for Digital CMOS-ICS","authors":"A. Rothermel, F. Dell'ova","doi":"10.1109/ESSCIRC.1992.5468148","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468148","url":null,"abstract":"A circuit is described for use in digital systems. It allows to measure the phase of incoming asynchronous signals relative to the system clock. The reference of the asynchronous signal is the positive or negative slope. Its phase is measured with a resolution of 1/32 of a system clock cycle (50 .. 75 ns). Timing precision is better than 200 ps without any adjustments. One external capacitor is needed.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"23 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114116688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Future of Battery Operated Systems 电池供电系统的未来
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468463
J. Rapeli
{"title":"Future of Battery Operated Systems","authors":"J. Rapeli","doi":"10.1109/ESSCIRC.1992.5468463","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468463","url":null,"abstract":"","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Floating-Point A/D Converter for Smart Sensors 用于智能传感器的浮点A/D转换器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468129
K. Mahmoud, R. Wolffenbuttel
{"title":"A Floating-Point A/D Converter for Smart Sensors","authors":"K. Mahmoud, R. Wolffenbuttel","doi":"10.1109/ESSCIRC.1992.5468129","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468129","url":null,"abstract":"A binary scaled programmable current source has been designed for use in a non-linear A/D converter for smart sensors applications. The non-linear conversion is achieved by using accurate binary-weighted current sources with emitter scaling and analog current switches. The A/D converter implements two programmable current sources, the first is used to determine the exponent, while the second is used to determine the mantissa in a floating point representation number. The current source and the required electronics are implemented using a bipolar process in silicon which makes it compatible with silicon sensors. A special layout has been implemented in the design to compensate for mismatch gradients over the chip.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115227463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power Low-Voltage Second-Order High-Pass Butterworth Leapfrog Filter 一种低功耗低电压二阶高通巴特沃斯跳越滤波器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468449
W. Serdijn
{"title":"A Low-Power Low-Voltage Second-Order High-Pass Butterworth Leapfrog Filter","authors":"W. Serdijn","doi":"10.1109/ESSCIRC.1992.5468449","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468449","url":null,"abstract":"A low-power bipolar continuous-time low-frequency high-pass second-order Butterworth filter that works in the current domain and operates from a single 1.3-V battery is presented. The filter contains two adjustable integrators. These integrators are realized by means of a capacitance and an adjustable transconductance amplifier with an indirect output. The complete filter, including all capacitances needed, can be integrated in a standard full-custom IC process. A semi-custom realization is shown. The filter demonstrates operation with battery voltages down to IV with less than 16¿W power consumption and a dynamic range of 50 dB. Its cutoff frequency can be varied exponentially with a control current from 100 Hz - 1kHz.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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