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ESSCIRC '92: Eighteenth European Solid-State Circuits conference最新文献

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Technology independent VLSI-Design using Bit Level self-timed circuits 采用位级自定时电路的技术独立vlsi设计
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468165
C. Heer, O. Aumann
{"title":"Technology independent VLSI-Design using Bit Level self-timed circuits","authors":"C. Heer, O. Aumann","doi":"10.1109/ESSCIRC.1992.5468165","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468165","url":null,"abstract":"In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5¿m- and a 0,8¿m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5¿m) up to 100 MHz (0,8¿m) have been measured for self-timed asynchronous test circuits.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116018741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
20 Gbit/s Integrated Laser Diode Voltage Driver Using 0.3 μm Gate Length Quantum Well Transistors 采用0.3 μm门长量子阱晶体管的20gbit /s集成激光二极管电压驱动器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468178
Z. Wang, M. Berroth, U. Nowotny, P. Hofmann, A. Hulsmann, G. Kaufel, K. Kohler, B. Raynor, J. Schneider
{"title":"20 Gbit/s Integrated Laser Diode Voltage Driver Using 0.3 μm Gate Length Quantum Well Transistors","authors":"Z. Wang, M. Berroth, U. Nowotny, P. Hofmann, A. Hulsmann, G. Kaufel, K. Kohler, B. Raynor, J. Schneider","doi":"10.1109/ESSCIRC.1992.5468178","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468178","url":null,"abstract":"An integrated laser diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with a gate length of 0.3 μm has been developed. Its large signal bandwidth was 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gbit/s showed an opening like that of the input signal. Increasing the bit rate of the input signal by means of a multiplexer, we can prove that the LDVD can operate at 20 Gbit/s. The maximum output current is over 90 mA; the maximum modulation voltage of 800 mV corresponds to 40 mA modulation current for a laser diode with 20 ¿ dynamic resistance. The power consumption is less than 500 mW.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131578729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Neuron- and a Synapse Chip for Artificial Neural Networks 用于人工神经网络的神经元和突触芯片
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468235
Jonathan Lansner, T. Lehmann
{"title":"A Neuron- and a Synapse Chip for Artificial Neural Networks","authors":"Jonathan Lansner, T. Lehmann","doi":"10.1109/ESSCIRC.1992.5468235","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468235","url":null,"abstract":"A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SeeHear System: A New Implementation SeeHear系统:一种新的实现
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468248
Yong Cao, S. Mattisson, Christian Bjork
{"title":"SeeHear System: A New Implementation","authors":"Yong Cao, S. Mattisson, Christian Bjork","doi":"10.1109/ESSCIRC.1992.5468248","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468248","url":null,"abstract":"A SeeHear system, based on a custom analog VLSI chip, has been designed, simulated, fabricated and experimentally tested. The design considerations are concentrated on the implementation of the analog delay lines, which are the key building blocks for implementing the binaural-headshadow and pinna-trague models of the SeeHear system. Allpass filter circuits, instead of follower-integrator (lowpass filter) circuits, are employed to implement the delay line, giving a wider bandwidth and ideal analog signal delay within the audio band. The chip, with 11×15 pixels, was fabricated by NORCHIP using a standard 1.2¿m N-well CMOS process.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122271632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High Resolution CMOS Current Comparators 高分辨率CMOS电流比较器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468214
R. Domínguez-Castro, Á. Rodríguez-Vázquez, F. Medeiro, J. L. Huertas
{"title":"High Resolution CMOS Current Comparators","authors":"R. Domínguez-Castro, Á. Rodríguez-Vázquez, F. Medeiro, J. L. Huertas","doi":"10.1109/ESSCIRC.1992.5468214","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468214","url":null,"abstract":"A 2¿m CMOS current comparator prototype is presented with an input current comparison range of 140dB and virtual zero offset(≪10pA). The circuit uses capacitive sensing for high resolution and nonlinear feedback to achieve small input voltage variations in the complete input current range. Operation speed for low current is abot two orders of magnitude larger than for conventional circuits. Simplified modeling issues are used to compare alternative comparator architectures.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131772990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Industrial Application of High Level Design Tools in Large Computer System Development 高级设计工具在大型计算机系统开发中的工业应用
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468455
J. Tual, H.N. Nguyen
{"title":"Industrial Application of High Level Design Tools in Large Computer System Development","authors":"J. Tual, H.N. Nguyen","doi":"10.1109/ESSCIRC.1992.5468455","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468455","url":null,"abstract":"This paper describes the current design methodologies in use at BULL S.A. for the development of high-range, general-purpose computers. These systems are characterized by a very complex architecture, implemented in VLSI circuits using up-to-date CMOS technologies. To meet the time to market constraints, well defined methodologies have to be applied, guarantying a one pass zero defect design at both the functional and performance levels. Since more than 10 years, advanced design tools have been developed in the Company, to deal with the underlying design challenges. More precisely this paper presents the most innovative parts of the current methodologies, as they have been or are used by the designers. A specific emphasis is put on high level description and verification methods and tools, usable for system complexities of several millions of gates. Finally the paper contains also some prospective views on the future of high-level design tools, as they can be viewed from a mainframe manufacturer point of view.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Photosensors for CMOS Pulsed Light Detectors 用于CMOS脉冲光探测器的光传感器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468201
T. Lande, Morten Salomonsen, Y. Berg, P. Pahr
{"title":"Photosensors for CMOS Pulsed Light Detectors","authors":"T. Lande, Morten Salomonsen, Y. Berg, P. Pahr","doi":"10.1109/ESSCIRC.1992.5468201","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468201","url":null,"abstract":"An integrated pulsed light detector with on-chip photosensors have been sucessfully fabricated in standard CMOS. Typical applications are index-hole detection in diskettedrives or end-of-tape holes in streamer tapes.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Parallel Analog CMOS Signal Processor for Image Contrast Enhancement 一种用于图像对比度增强的并行模拟CMOS信号处理器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468271
T. Shimmi, H. Kobayashi, Tetsuya Yagi, T. Sawaji, T. Matsumoto, Asad A. Abidi
{"title":"A Parallel Analog CMOS Signal Processor for Image Contrast Enhancement","authors":"T. Shimmi, H. Kobayashi, Tetsuya Yagi, T. Sawaji, T. Matsumoto, Asad A. Abidi","doi":"10.1109/ESSCIRC.1992.5468271","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468271","url":null,"abstract":"A 2D analog CMOS network with a 53 × 52 array of embedded photosensors implements a convolution function approximating the Laplacian of a Gaussian. Experimental results verify that high quality contrast enhancement of images of simple objects may be obtained in analog circuits with careful circuit design. The 7.9 × 9.2 mm IC dissipates 350 mW from a 5 V power supply.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124822498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Pattern Recognition Demonstrator based on a Silicon Neural Chip 基于硅神经芯片的模式识别演示器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468242
D. Del Corso, F. Gregoretti, L. Reyneri, A. Allasia
{"title":"A Pattern Recognition Demonstrator based on a Silicon Neural Chip","authors":"D. Del Corso, F. Gregoretti, L. Reyneri, A. Allasia","doi":"10.1109/ESSCIRC.1992.5468242","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468242","url":null,"abstract":"This paper describes a self-standing hardware pattern recognition system based on neural algorithms. The system uses a dedicated VLSI neural chip which implements a vector-matrix multiplier built of an array of 16 × 8 multiplying D/A converters with an 8-bit digital storage cell each. The conversion principle is based on an aperiodic clock which rotates data through a weighting shift register. A prototype chip has been fabricated, tested and assembled together with an array of photodetectors for simple image recognition purposes. The system has been conceived as a stand-alone demonstrator of pattern recognition capabilites of Artificial Neural Networks.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131284741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A GSM Vocoder using a flexible DSP core GSM声码器使用灵活的DSP核心
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468230
M. Cand, B. Conq, M. Soler, B. Bocaert, A. Kuntz
{"title":"A GSM Vocoder using a flexible DSP core","authors":"M. Cand, B. Conq, M. Soler, B. Bocaert, A. Kuntz","doi":"10.1109/ESSCIRC.1992.5468230","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468230","url":null,"abstract":"We present a speech vocoder that will be used in GSM mobile systems to convert 300-3400 Hz speech to 13 Kbit/s digital bit stream. This 350 000 transistor chip was designed in a CMOS 1.0 ¿m technology in collaboration with VLSI Technology. The architecture was defined with a flexible 13 MHz DSP core developped at CNET. The GSM 06 series recommendations are met with a low 2.7 MIps. The DSP core has a VLIW microprogrammed Harvard architecture. The ROM program is obtained without writing assembler using a C-to-microcode compiler targeted to the architecture.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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