发布求助
文献互助 智能选刊 最新文献

ESSCIRC '92: Eighteenth European Solid-State Circuits conference最新文献

筛选
英文 中文
A Low-Power 8 Bit 13.5 MHz Video CMOS ADC for Visiophony ISDN Applications 用于可视ISDN应用的低功耗8位13.5 MHz视频CMOS ADC
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468427
A. Abrial, J. Bouvier, J. Fournier, P. Senn
{"title":"A Low-Power 8 Bit 13.5 MHz Video CMOS ADC for Visiophony ISDN Applications","authors":"A. Abrial, J. Bouvier, J. Fournier, P. Senn","doi":"10.1109/ESSCIRC.1992.5468427","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468427","url":null,"abstract":"this paper describes a half-flash subranging video 13.5 MHz ADC using a new architecture which allows a flash conversion rate without any extra multiplexing comparators.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134288651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Analog CMOS Multiplier Based on the Tomota-Sugiyama-Yamaguchi Principle 基于tomoto - sugiyama - yamaguchi原理的模拟CMOS乘法器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468147
B.A. De Cock, D. Maurissens, J. Cornelis
{"title":"An Analog CMOS Multiplier Based on the Tomota-Sugiyama-Yamaguchi Principle","authors":"B.A. De Cock, D. Maurissens, J. Cornelis","doi":"10.1109/ESSCIRC.1992.5468147","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468147","url":null,"abstract":"A CMOS pulse width modulator/pulse amplitude modulator (PWM/PAM) has been realised. The design is based on the Tomota-Sugiyama-Yamaguchi (TSY)-principle. The PWM/PAM has been used to build a four quadrant analog multiplier (4-QAM) with a DC transfer function which depends only on resistor matching and on the value of a reference voltage. The PWM/PAM circuit was fabricated in a 3-¿m CMOS process. Measurements show a small total error (max. 2%) without trimming. A DC-error model, a stability criterion and a bandwidth restriction are derived.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114296641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture 一个622Mbps 8×8 ATM交换芯片组与共享多缓冲区架构
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468236
H. Kondoh, H. Notani, H. Yamanaka, K. Higashitani, H. Saito, I. Hayashi, S. Kohama, Y. Matsuda, K. Oshima, M. Nakaya
{"title":"A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture","authors":"H. Kondoh, H. Notani, H. Yamanaka, K. Higashitani, H. Saito, I. Hayashi, S. Kohama, Y. Matsuda, K. Oshima, M. Nakaya","doi":"10.1109/ESSCIRC.1992.5468236","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468236","url":null,"abstract":"An ATM (Asynchronous Transfer Mode) switch chip set utilizing the Shared Multi-Buffer architecture is described. While keeping the high buffer utilization efficiency, required access time for the buffer is greatly reduced compared with the conventional shared buffer type switches. This feature enables the high speed operation of the switch. Four Aligner-LSI's, bit sliced nine Buffer-Switch-LSI's and one Control-LSI construct a 622Mbps 8×8 ATM switch system operating at 78MHz. Using the time sharing method, 622Mbps and 155Mbps channels can be exchanged at a time.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114478071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
R&D in Analog Circuits: Possibilities and Needed Support 模拟电路的研发:可能性和所需的支持
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468477
Y. Tsividis
{"title":"R&D in Analog Circuits: Possibilities and Needed Support","authors":"Y. Tsividis","doi":"10.1109/ESSCIRC.1992.5468477","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468477","url":null,"abstract":"It is argued that the importance of analog and mixed-analog-digital integrated circuits has increased in terms of volume and in terms of the number of applications, as analog circuits accompany the computer wherever the latter must interface with the real world. A number of important applications are identified, and several examples of open R&D topics are given. The context and nature of analog circuit R&D are discussed, and several factors that hinder such R&D are examined. These include some factors which are non-technical in nature but are of no lesser importance than the technical ones.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122239366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation Based Automated Analog Design using Statistical Optimization 基于统计优化的仿真自动化模拟设计
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468202
F. Medeiro, Á. Rodríguez-Vázquez, R. Domínguez-Castro, J. L. Huertas
{"title":"Simulation Based Automated Analog Design using Statistical Optimization","authors":"F. Medeiro, Á. Rodríguez-Vázquez, R. Domínguez-Castro, J. L. Huertas","doi":"10.1109/ESSCIRC.1992.5468202","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468202","url":null,"abstract":"A cost function structure and innovative heuristics are given for the automated design of analog cells using statistical optimization in a simulation based approach. DC solution strategies are used to reduce CPU time. The technique allows to size complex circuits starting from scratch within reasonable CPU time. A 2¿m CMOS prototype of a 48 transistors fully differential opamp for a second order over-sampled modulator is presented demonstrating suitability of the technique.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5V CMOS Programmable Acoustic Front-End for ISDN Terminals and Digital Telephone Sets 用于ISDN终端和数字电话机的5V CMOS可编程声学前端
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468221
G. Nicollini, P. Confalonieri, C. Crippa, S. Pernici, Y. Mazoyer, C. Dallavalle, S. Mariani, A. Calloni
{"title":"A 5V CMOS Programmable Acoustic Front-End for ISDN Terminals and Digital Telephone Sets","authors":"G. Nicollini, P. Confalonieri, C. Crippa, S. Pernici, Y. Mazoyer, C. Dallavalle, S. Mariani, A. Calloni","doi":"10.1109/ESSCIRC.1992.5468221","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468221","url":null,"abstract":"A 5V programmable acoustic front-end IC for ISDN terminal and digital telephone set applications is presented. The chip performs PCM codec and filter functions fulfilling and exceeding all D3/D4 and CCITT specs. It implements the analog interfaces required for the speech (low noise microphone preamplifier, earpiece and loudspeaker drivers, sidetone, antilarsen control) and tone/ring/DTMF generation without external components. The device can be controlled by a microprocessor or a HDLC controller via a separate four wire control interface or by means of a serial control channel multiplexed with the PCM voice/data in a GCI compatible format. Chip area is 30 mm2 in a 1.5¿ CMOS technology. Active/stand-by power consumption is 60mW/0.2mW from a single 5V supply.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129681584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 16-channel Readout Chip - A new sparse data readout architecture 一种16通道读出芯片——一种新的稀疏数据读出架构
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468222
P. Murray, M. Lovell
{"title":"A 16-channel Readout Chip - A new sparse data readout architecture","authors":"P. Murray, M. Lovell","doi":"10.1109/ESSCIRC.1992.5468222","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468222","url":null,"abstract":"This paper describes a new architecture for performing data compression on a large matrix of parallel digital inputs, only a small proportion of which carries a logical `1'. The system assigns a unique address to each of the active inputs (suppressing the inactive ones) and feeds them serially onto a data bus. The architecture is implemented using an array of CMOS digital signal processing ASICs, which have been designed at R.A.L, England and tested at C.E.R.N. in Geneva.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125610733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS 155 MHz Clock-Frame Recovery IC for SONET/SDH Application 用于SONET/SDH应用的CMOS 155 MHz时钟帧恢复IC
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468184
Z. Chang, A. Delarbre, C. Gouwy, K. Schelfhout, J. Haspeslagh, P. Reusens
{"title":"A CMOS 155 MHz Clock-Frame Recovery IC for SONET/SDH Application","authors":"Z. Chang, A. Delarbre, C. Gouwy, K. Schelfhout, J. Haspeslagh, P. Reusens","doi":"10.1109/ESSCIRC.1992.5468184","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468184","url":null,"abstract":"A CMOS 155.5 MHz clock-frame recovery IC for use in SONET/SDH environments is presented. The IC is a mixed analog/digital circuit with ECL-like input/output and is capable of handling signals up to 180 MHz. The chip has two functions : regeneration of the 155.5 MHz clock at ECL levels and recovery of frame signals from a modulated 155.5 MHz low level input signal. The clock regeneration is realized by an analog approach, while the frame recovery is implemented using digital techniques. The total analog path, containing a novel ECL-CMOS, the clock regeneration and CMOS-ECL converters, is designed to keep the maximum peak clock jitter lower than 300 ps and the rms jitter below 70 ps. The chip is fabricated in a 1.2¿m CMOS process measuring a 35 mm2 silicon area. The chip is powered by a single 5 V supply and consumes 2 W under maximal load condition.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123683438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Four Channel Half Duplex FSK Modem for Communication on Power Lines 电力线通信用四通道半双工FSK调制解调器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468229
S. Ramet, J. Lebrun
{"title":"A Four Channel Half Duplex FSK Modem for Communication on Power Lines","authors":"S. Ramet, J. Lebrun","doi":"10.1109/ESSCIRC.1992.5468229","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468229","url":null,"abstract":"A versatile four channel FSK modem operating in the 65 to 90 kHz band has been developed for communications on the power line network. It uses direct frequency synthesis to generate the Tx signal and automatically tuned SCF's in both the Tx and Rx paths. At the minimum receive sensitivity (2 mVrms) the BER is 10¿5 with a SNR of 15 dB.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Dynamic Range Wide-Band Integrated Receiver for Optical Transmission Using a Gain Switch at the Input 输入端采用增益开关的高动态范围宽带集成光传输接收机
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468177
L. van den Broeke, A. J. Nieuwkerk
{"title":"High-Dynamic Range Wide-Band Integrated Receiver for Optical Transmission Using a Gain Switch at the Input","authors":"L. van den Broeke, A. J. Nieuwkerk","doi":"10.1109/ESSCIRC.1992.5468177","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468177","url":null,"abstract":"The front-end of optical transmission systems usually consists of a low-noise wide-band negative-feedback transimpedance or current-amplifier. The dynamic range of this type of amplifier can be extended considerably by using a low-noise current-switch at the input of the amplifier. This switch bypasses large input signals directly to the output. The design strategy of both the switch and the amplifier is presented. A complete receiver, having a dynamic range of 83dB in a bandwidth of 220MHz and consuming a supply current of 1.5mA, is realized in a 2.5GHz bipolar technology.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信