{"title":"一种16通道读出芯片——一种新的稀疏数据读出架构","authors":"P. Murray, M. Lovell","doi":"10.1109/ESSCIRC.1992.5468222","DOIUrl":null,"url":null,"abstract":"This paper describes a new architecture for performing data compression on a large matrix of parallel digital inputs, only a small proportion of which carries a logical `1'. The system assigns a unique address to each of the active inputs (suppressing the inactive ones) and feeds them serially onto a data bus. The architecture is implemented using an array of CMOS digital signal processing ASICs, which have been designed at R.A.L, England and tested at C.E.R.N. in Geneva.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 16-channel Readout Chip - A new sparse data readout architecture\",\"authors\":\"P. Murray, M. Lovell\",\"doi\":\"10.1109/ESSCIRC.1992.5468222\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a new architecture for performing data compression on a large matrix of parallel digital inputs, only a small proportion of which carries a logical `1'. The system assigns a unique address to each of the active inputs (suppressing the inactive ones) and feeds them serially onto a data bus. The architecture is implemented using an array of CMOS digital signal processing ASICs, which have been designed at R.A.L, England and tested at C.E.R.N. in Geneva.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468222\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468222","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 16-channel Readout Chip - A new sparse data readout architecture
This paper describes a new architecture for performing data compression on a large matrix of parallel digital inputs, only a small proportion of which carries a logical `1'. The system assigns a unique address to each of the active inputs (suppressing the inactive ones) and feeds them serially onto a data bus. The architecture is implemented using an array of CMOS digital signal processing ASICs, which have been designed at R.A.L, England and tested at C.E.R.N. in Geneva.
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