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ESSCIRC '92: Eighteenth European Solid-State Circuits conference最新文献

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Color Burst PLL for Digital Combfilter Decoder 用于数字混合滤波解码器的彩色突发锁相环
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468159
H. Schemmann, M. Shumila, J. Armer
{"title":"Color Burst PLL for Digital Combfilter Decoder","authors":"H. Schemmann, M. Shumila, J. Armer","doi":"10.1109/ESSCIRC.1992.5468159","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468159","url":null,"abstract":"This paper describes a circuit to generate the color burst locked systemclock for a digital videoprocessor IC. A new PLL system including a voltage controlled crystal oscillator was designed. The approach chosen includes all functions on chip and is adjustment free. A capture range of +/- 9.6 kHz at 17.733 MHz center frequency was measured with first prototype ICs.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area and Timing Optimisation of high performant datapaths with CHOPIN-2 基于CHOPIN-2的高性能数据路径的面积和时间优化
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468189
L. Rijnders, Z. Sahraoui, P. Six, H. de Man
{"title":"Area and Timing Optimisation of high performant datapaths with CHOPIN-2","authors":"L. Rijnders, Z. Sahraoui, P. Six, H. de Man","doi":"10.1109/ESSCIRC.1992.5468189","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468189","url":null,"abstract":"High throughput applications require dedicated datapaths. Their performance can be improved by selecting an appropriate logic implementation and by optimising the number and position of pipeline registers. The CHOPIN-2 toolbox provides the user with the possibility to generate a number of design alternatives and optimise the clock speed. The CHOPIN-2 system has been implemented and tested on a number of industrial datapaths.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116585357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 33-ns 64-Mb DRAM with Master-Wordline Architecture 采用主字线结构的33-ns 64-Mb DRAM
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468392
D. Galbi, Klaus Althoff, R. Parent, O. Kiehl, R. Houghton, F. Bonner, M. Killian, A. Wilson, K. Lau, M. Clinton, D. Chapman, Horst Fischer
{"title":"A 33-ns 64-Mb DRAM with Master-Wordline Architecture","authors":"D. Galbi, Klaus Althoff, R. Parent, O. Kiehl, R. Houghton, F. Bonner, M. Killian, A. Wilson, K. Lau, M. Clinton, D. Chapman, Horst Fischer","doi":"10.1109/ESSCIRC.1992.5468392","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468392","url":null,"abstract":"A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122767636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A High Performance RSA Encryption Processor in SOI and Bulk CMOS Technologies 基于SOI和批量CMOS技术的高性能RSA加密处理器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468213
P. Ivey, S. Walker, J. Stern, S. Davidson
{"title":"A High Performance RSA Encryption Processor in SOI and Bulk CMOS Technologies","authors":"P. Ivey, S. Walker, J. Stern, S. Davidson","doi":"10.1109/ESSCIRC.1992.5468213","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468213","url":null,"abstract":"This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of 512 bits. The chips, which are 6.2 by 4.2 millimetres and contain 50,000 gates, have been designed in a 0.7 micron CMOS, silicon on insulator process and in a 0.7 micron bulk CMOS process. The chips are functionally identical and each form a self contained subsystem which interfaces directly to standard microprocessors. The design of the two chips was carried out in order to directly compare the two silicon processes. SOI is found to perform 50% faster, consume 30% less power and occupy approximately the same area as the bulk device.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116831619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The NCP Retina: An Imager, a Halftoner and a Micro-Grained Array Processor on the Same Chip NCP视网膜:同一芯片上的成像仪、半调色剂和微粒度阵列处理器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468374
T. Bernard, B. Zavidovique, F. Devos
{"title":"The NCP Retina: An Imager, a Halftoner and a Micro-Grained Array Processor on the Same Chip","authors":"T. Bernard, B. Zavidovique, F. Devos","doi":"10.1109/ESSCIRC.1992.5468374","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468374","url":null,"abstract":"An electronic retina is a device which intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environnements and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to three bits, we have demonstrated both the technological practicality and the computational efficiency of this \"boolean retina\" concept. Using semi-static shifting structures and tricky circuitry, a minimal retina boolean processor can be built with less than 30 transistors and controlled by as few as 5 global clock signals. The successful design, integration and test of such a 65×76 boolean retina on a 50 mm2 CMOS 2¿m circuit are presented.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130496242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Applications of Mixed Analog/Digital Design 模拟/数字混合设计的应用
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468470
B. Hosticka
{"title":"Applications of Mixed Analog/Digital Design","authors":"B. Hosticka","doi":"10.1109/ESSCIRC.1992.5468470","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468470","url":null,"abstract":"Design of a large mixed analog/digital high-performance system on a silicon chip is a challenge for any IC designer, but it can become easily a nightmare. It is, therefore, very important to know precisely what analog/digital combination means for the circuit design and performance. In this contribution, we will review fundamentals of mixed design and discuss its merits and pitfalls.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129289626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SUNBAR - A Universal Boundary Scan Architecture for a Sea-of-Gates Semi-Custom Environment 用于海门半定制环境的通用边界扫描架构
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468166
T. Buchner, E. Bernath, R. Gurkasch, T. Schwederski, H. Werkmann
{"title":"SUNBAR - A Universal Boundary Scan Architecture for a Sea-of-Gates Semi-Custom Environment","authors":"T. Buchner, E. Bernath, R. Gurkasch, T. Schwederski, H. Werkmann","doi":"10.1109/ESSCIRC.1992.5468166","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468166","url":null,"abstract":"A concept for a Standardized Universal Boundary Scan Architecture for semi-custom sea-of-gates ASICs (SUNBAR) is presented that complies with the IEEE 1149.1 standard and is extensible in a flexible way to control and observe a built-in (self) test of complex circuits. Using a fixed, extensible part with basic boundary scan functions integrated as a full custom circuitry on the master, and a part with enhanced functions placed on the semi-custom core of the chip, the architecture combines high flexibility with low area consumption. Besides its boundary scan functionality, SUNBAR can be used as a front-end for structured design-for-testability measures like multiple scan paths, macro testing via hierarchical test controllers, BIST using PRPG/PSA circuitry, etc. SUNBAR supports all testable designs on the IMS Gate Forest, a 1.2¿m sea-of-gates array.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"130 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124247544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 40×40 CCD/CMOS AVD Processor for Use in a Stereo Vision System 用于立体视觉系统的40×40 CCD/CMOS AVD处理器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468373
J. Mikko Hakkarainen, H. Lee
{"title":"A 40×40 CCD/CMOS AVD Processor for Use in a Stereo Vision System","authors":"J. Mikko Hakkarainen, H. Lee","doi":"10.1109/ESSCIRC.1992.5468373","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468373","url":null,"abstract":"This paper presents an analog VLSI processor chip with application in a high-speed binocular stereo vision system used for the recovery of scene depth. We have attempted to exploit the principal advantages of analog VLSI - small area, high speed, and low power - while minimizing the effects of its traditional disadvantages - limited accuracy, inflexibility, and lack of storage capacity. A CCD/CMOS stereo system implementation is proposed, capable of processing several thousand image frame pairs per second for 40×40 pixel binocular images. A 40×40 pixel absolute-value-of-difference (AVD) array, the core processor of the stereo system, was fabricated in a 2 ¿m CCD/CMOS process. Individual unit cells in the array were characterized and tested. The array functionality was next tested by imbedding it in a computurized stereo system and using both real scene and computer generated input image pairs. The system output was compared with full computer simulations for the same image pairs, showing good correlation.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121574071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield optimization of analog ICs using 2-step analytic modeling methods 用两步解析建模方法优化模拟集成电路的良率
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468265
C. Guardiani, Primo Scandolara, J. Benkoski, G. Nicollini
{"title":"Yield optimization of analog ICs using 2-step analytic modeling methods","authors":"C. Guardiani, Primo Scandolara, J. Benkoski, G. Nicollini","doi":"10.1109/ESSCIRC.1992.5468265","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468265","url":null,"abstract":"We applied two innovative methods for statistical design optimization in the design of a CMOS OP-AMP. The most important feature of these methods is the derivation of an analytic function representing the yield surface in the design parameters space. All the required operations are implemented in an integrated CAD system and fully automatized. The results are compared with measures on several wafer lots.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132272536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Yield: High Performance Analog Circuit Design With Regard To Statistical Aspects 产量:基于统计方面的高性能模拟电路设计
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468272
R. WeiBenfels, J. Oehm, K. Schumacher
{"title":"Yield: High Performance Analog Circuit Design With Regard To Statistical Aspects","authors":"R. WeiBenfels, J. Oehm, K. Schumacher","doi":"10.1109/ESSCIRC.1992.5468272","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468272","url":null,"abstract":"A novel approach to the computer supported design of high performance analog circuits is presented. Circuit design and dimensioning is effectuated utilizing procedural descriptions of the designer's own techniques and given libraries, according to designer-given specifications. Thus the designer is enabled to concentrate on an increased number of inter-dependences between the circuit's properties and specifications than would be possible using manual calculation or fully automatic design systems. Free programmability and an open model interface give flexibility as well as improved design accuracy and novel means of analysis. Taking into account noise and statistical local and global matching calculations the designer can incorporate yield aspects into the design flow. The usage of the YIELD design tool is demonstrated by dimensioning a patented temperature compensated, resistorless, precision current reference with regard to local matching.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125836237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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