A 33-ns 64-Mb DRAM with Master-Wordline Architecture

Abstract

A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.