T. Buchner, E. Bernath, R. Gurkasch, T. Schwederski, H. Werkmann
{"title":"SUNBAR - A Universal Boundary Scan Architecture for a Sea-of-Gates Semi-Custom Environment","authors":"T. Buchner, E. Bernath, R. Gurkasch, T. Schwederski, H. Werkmann","doi":"10.1109/ESSCIRC.1992.5468166","DOIUrl":null,"url":null,"abstract":"A concept for a Standardized Universal Boundary Scan Architecture for semi-custom sea-of-gates ASICs (SUNBAR) is presented that complies with the IEEE 1149.1 standard and is extensible in a flexible way to control and observe a built-in (self) test of complex circuits. Using a fixed, extensible part with basic boundary scan functions integrated as a full custom circuitry on the master, and a part with enhanced functions placed on the semi-custom core of the chip, the architecture combines high flexibility with low area consumption. Besides its boundary scan functionality, SUNBAR can be used as a front-end for structured design-for-testability measures like multiple scan paths, macro testing via hierarchical test controllers, BIST using PRPG/PSA circuitry, etc. SUNBAR supports all testable designs on the IMS Gate Forest, a 1.2¿m sea-of-gates array.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"130 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468166","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A concept for a Standardized Universal Boundary Scan Architecture for semi-custom sea-of-gates ASICs (SUNBAR) is presented that complies with the IEEE 1149.1 standard and is extensible in a flexible way to control and observe a built-in (self) test of complex circuits. Using a fixed, extensible part with basic boundary scan functions integrated as a full custom circuitry on the master, and a part with enhanced functions placed on the semi-custom core of the chip, the architecture combines high flexibility with low area consumption. Besides its boundary scan functionality, SUNBAR can be used as a front-end for structured design-for-testability measures like multiple scan paths, macro testing via hierarchical test controllers, BIST using PRPG/PSA circuitry, etc. SUNBAR supports all testable designs on the IMS Gate Forest, a 1.2¿m sea-of-gates array.