{"title":"A CMOS Resistive-fuse Processor for 2-D Image Acquisition, Smoothing, and Segmentation","authors":"P. Yu, Hae-Seung Lee","doi":"10.1109/ESSCIRC.1992.5468379","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468379","url":null,"abstract":"An integrated CMOS resistive-fuse processor capable of smoothing out noise while preserving the edges of a 32×32 image is described. An on-chip photo-transistor imager converts the optical image into electrical currents. The design of a single-pixel processing element using resistive fuses is described. The processed output is read out using a row decoder and a column MUX. Operating from a single 5-V supply, the chip typically dissipates only 10 mW.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124767781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Comparison of DC and Transient Response Tests for Analogue Circuits","authors":"D. Taylor, P. Evans, T. I. Pritchard","doi":"10.1109/ESSCIRC.1992.5468407","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468407","url":null,"abstract":"Transient Response Analysis [1] (TRA) is a quick and inexpensive method of testing analogue circuitry. In this paper we compare the effectiveness of traditional DC testing of analogue circuit cells with dynamic tests, using a simple analogue subcircuit element which models one component of a large mixed-signal ASIC.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130612973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A broad bandwidth mixed analog/digital integrated circuit for measuring complex impedances; Principles and design considerations","authors":"M. A. Hilhorst, J. Balendonck, F. Kampers","doi":"10.1109/ESSCIRC.1992.5468141","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468141","url":null,"abstract":"A broad bandwidth measuring system for complex impedances is presented. The measuring principle, based on synchronous detection, is worked out mathematical. The final circuit is realized as a mixed analog/digital BiCMOS integrated circuit. The output of the IC is a modulated 100 kHz frequency and RS232. The phase accuracy requirement of the system is mainly determined by parameter deviation of transistors which share the same IC. The phase accuracy of the circuit is according to PSPICE simulations 0.07° at 20 MHz. This enables to measure a capacitance of 100 pF, in parallel with a conductance of 100 mS, with an accuracy of ± 1 pF. The requirements are based on the application of the IC in a sensor for water content and ionic concentration measurements ments in soil or other agricultural substrates.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132499396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Short Term Analogue Memory","authors":"P. Shah","doi":"10.1109/ESSCIRC.1992.5468400","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468400","url":null,"abstract":"A short term analogue memory is described. It is based on a well-known sample-hold topology in which leakage currents have been minimized partly by circuit design and partly by layout techniques. Measurements on a test chip implemented in a standard 2.4 micron analogue CMOS process show a droop rate of 0.075mV per second with a 1pF hold capacitor. This is equivalent to a retention time of approximately 1¿ minute with 10 bits accuracy, assuming a full scale of +/-3.5V. It is expected that this can be improved by more than an order of magnitude by improving the layout of the hold capacitor. Thus hold times of several hours should be achievable with moderate capacitance values.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121219178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI Realization of 2D HDTV Subband Filterbanks with on-Chip Line Memories and FIFOs","authors":"K. Gruger, M. Winzker, W. Gehrke, P. Pirsch","doi":"10.1109/ESSCIRC.1992.5468153","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468153","url":null,"abstract":"Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14×10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2¿m-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134044785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Laser driver IC in Si-bipolar technology for 5 Gbit/s and 45 mA modulation current","authors":"R. Derksen, H. Wernz","doi":"10.1109/ESSCIRC.1992.5468171","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468171","url":null,"abstract":"We report on the design and implementation of a 5 Gbit/s-silicon bipolar laser driver IC for direct modulation of a laser diode. The adjustable modulation current range is 15 mA - 45 mA. The IC can drive 25 ¿-laser modules via a 25 ¿-line. Typical power dissipation is 930 mW for a modulation current of 45 mA. Though the IC has been fabricated on a production line instead of using a lab technology, it is one of the fastest laser driver ICs in silicon. In contrast to previous works in this field, not only the capability to drive an ohmic load is shown, but also the performance in the case of driving a real laser module.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134202060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Balestro, C. Joanblanq, S. Maginot, M. Remy, P. Senn, J. Bernoux, M. Lanoiselée, J. Palicot, J. Veillard
{"title":"A D2-MAC/packet Equalizer","authors":"F. Balestro, C. Joanblanq, S. Maginot, M. Remy, P. Senn, J. Bernoux, M. Lanoiselée, J. Palicot, J. Veillard","doi":"10.1109/ESSCIRC.1992.5468160","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468160","url":null,"abstract":"The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 ¿m technology and is at this time being used in a D2-MAC reception environment.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116156887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"OPTIC - A High Performance Image Processor","authors":"P. Maguire, F. Griffin, M. O'sullivan, J. O'Brien","doi":"10.1109/ESSCIRC.1992.5468386","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468386","url":null,"abstract":"The OPTIC is a high performance VLSI device designed for use in general-purpose real-time vision systems. The chip incorporates a fast proprietary (see [1]) shape-and edge-recognition algorithm, which does not require any preprocessing of the grey-level image. This makes the device especially suited to difficult machine vision problems where the image quality varies over time. The full-custom 1.5¿m CMOS circuit contains 80,000 transistors and operates at an image sampling rate of 25MHz.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124470993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Circuit for GCD and Extended GCD Calculation With Unlimited Precision","authors":"R. Bouraoui, A. Guyot","doi":"10.1109/ESSCIRC.1992.5468172","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468172","url":null,"abstract":"In this paper, we present the architecture and implementation of a new algorithm to find the greatest common divisor (GCD) and extended GCD of very large integers (≫ 600 decimal digits). The method uses an internal radix 2 redundant representation and supports multiple precision. In addition, the design methodology was to find the best trade-offs between computation time and area.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"54 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simplified Low-Voltage and Low-Power Bipolar OpAmp with Non-linear Class-AB Rail-to-Rail Output Stage","authors":"Martijn Bredius, J. H. Huijsing","doi":"10.1109/ESSCIRC.1992.5468247","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468247","url":null,"abstract":"A simplified low-voltage and low-power bipolar OpAmp is presented using a non-linear class-AB control and rail-to-rail output stage. The circuit operates on supply voltages down to 1V. This OpAmp is intended for use as an on-chip building block and contains only 38 transistors. The OpAmp is successsfully realised in a semi-custom process with lateral PNPs. The measured 0dB gain bandwidth is 580kHz. The OpAmp can deliver +1.3mA/¿1.7mA maximum output current, while the quiescent current of the total circuit is only 70¿A.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121071233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}