VLSI Realization of 2D HDTV Subband Filterbanks with on-Chip Line Memories and FIFOs

Abstract

Subband coding is frequently proposed for source coding of HDTV. Key components for the compact realization of subband codecs are VLSI filterbanks for analysis and synthesis filtering. Avoiding programmability the development and application of dedicated subband filterbanks can significantly reduce hardware expense. For 2D Quadrature Mirror Filterbanks with 14×10 taps, a chip set with on-chip line memories and synchronous FIFOs has been developed using a 1.2¿m-CMOS technology. Only two identical ICs each with about 450,000 transistors and a chip area of 92mm2 are necessary for one filterbank. The implementation is adapted to the systems parameters of interlaced scanning but the architecture can easily be extended to the processing of future progressive HDTV.