F. Balestro, C. Joanblanq, S. Maginot, M. Remy, P. Senn, J. Bernoux, M. Lanoiselée, J. Palicot, J. Veillard
{"title":"一个D2-MAC/数据包均衡器","authors":"F. Balestro, C. Joanblanq, S. Maginot, M. Remy, P. Senn, J. Bernoux, M. Lanoiselée, J. Palicot, J. Veillard","doi":"10.1109/ESSCIRC.1992.5468160","DOIUrl":null,"url":null,"abstract":"The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 ¿m technology and is at this time being used in a D2-MAC reception environment.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A D2-MAC/packet Equalizer\",\"authors\":\"F. Balestro, C. Joanblanq, S. Maginot, M. Remy, P. Senn, J. Bernoux, M. Lanoiselée, J. Palicot, J. Veillard\",\"doi\":\"10.1109/ESSCIRC.1992.5468160\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 ¿m technology and is at this time being used in a D2-MAC reception environment.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468160\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 ¿m technology and is at this time being used in a D2-MAC reception environment.
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