A High Performance RSA Encryption Processor in SOI and Bulk CMOS Technologies

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of 512 bits. The chips, which are 6.2 by 4.2 millimetres and contain 50,000 gates, have been designed in a 0.7 micron CMOS, silicon on insulator process and in a 0.7 micron bulk CMOS process. The chips are functionally identical and each form a self contained subsystem which interfaces directly to standard microprocessors. The design of the two chips was carried out in order to directly compare the two silicon processes. SOI is found to perform 50% faster, consume 30% less power and occupy approximately the same area as the bulk device.