D. Galbi, Klaus Althoff, R. Parent, O. Kiehl, R. Houghton, F. Bonner, M. Killian, A. Wilson, K. Lau, M. Clinton, D. Chapman, Horst Fischer
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A 33-ns 64-Mb DRAM with Master-Wordline Architecture
A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.