H. Kondoh, H. Notani, H. Yamanaka, K. Higashitani, H. Saito, I. Hayashi, S. Kohama, Y. Matsuda, K. Oshima, M. Nakaya
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A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture
An ATM (Asynchronous Transfer Mode) switch chip set utilizing the Shared Multi-Buffer architecture is described. While keeping the high buffer utilization efficiency, required access time for the buffer is greatly reduced compared with the conventional shared buffer type switches. This feature enables the high speed operation of the switch. Four Aligner-LSI's, bit sliced nine Buffer-Switch-LSI's and one Control-LSI construct a 622Mbps 8×8 ATM switch system operating at 78MHz. Using the time sharing method, 622Mbps and 155Mbps channels can be exchanged at a time.
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