A CMOS 155 MHz Clock-Frame Recovery IC for SONET/SDH Application

Abstract

A CMOS 155.5 MHz clock-frame recovery IC for use in SONET/SDH environments is presented. The IC is a mixed analog/digital circuit with ECL-like input/output and is capable of handling signals up to 180 MHz. The chip has two functions : regeneration of the 155.5 MHz clock at ECL levels and recovery of frame signals from a modulated 155.5 MHz low level input signal. The clock regeneration is realized by an analog approach, while the frame recovery is implemented using digital techniques. The total analog path, containing a novel ECL-CMOS, the clock regeneration and CMOS-ECL converters, is designed to keep the maximum peak clock jitter lower than 300 ps and the rms jitter below 70 ps. The chip is fabricated in a 1.2¿m CMOS process measuring a 35 mm2 silicon area. The chip is powered by a single 5 V supply and consumes 2 W under maximal load condition.