发布求助
文献互助 智能选刊 最新文献

ESSCIRC '92: Eighteenth European Solid-State Circuits conference最新文献

筛选
英文 中文
Current controlled multi-step CMOS video data converters 电流控制的多步CMOS视频数据转换器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468435
L. Hanssen
{"title":"Current controlled multi-step CMOS video data converters","authors":"L. Hanssen","doi":"10.1109/ESSCIRC.1992.5468435","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468435","url":null,"abstract":"A method of connecting K identical parallel M bit converters to form a K-M bit converter is presented. By controlling the voltage drop over the resistor string with a current the linearity is made independent of offset voltage between the steps and high ONresistance in the switches. This connection gives DACs with linearity determined by the resistors and with a speed / power ratio of 15MHz/mW. An ADC based on the same idea has been developed for a PAL video application. This ADC uses two identical flash ADC blocks in the two-steps, making the principle suitable for monolithic integrated, hybrid and PCB solutions.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"286 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114184103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simplified Class AB Control Circuits for Rail to Rail Output Stages of Operational Amplifiers 运算放大器轨对轨输出级的简化AB类控制电路
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468260
W. Renirie, J. H. Huijsing
{"title":"Simplified Class AB Control Circuits for Rail to Rail Output Stages of Operational Amplifiers","authors":"W. Renirie, J. H. Huijsing","doi":"10.1109/ESSCIRC.1992.5468260","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468260","url":null,"abstract":"A new approach to solving the problem of class AB control of rail to rail output stages is presented. Step by step five simple class AB control circuits will be discussed, showing the advantages of 'common mode feed parallel'. One of the control circuits has been implemented in a simplified two stage OPAMP with a 2.5MHz bandwith, rail to rail output range and an input common mode range down to the negative rail. A photomicrograph as well as measurement results of a semicustom design are included.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126812953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A High-Speed, Threshold-Voltage-Mismatch Compensation Sense Amplifier for Gb-scale DRAM Arrays 用于gb级DRAM阵列的高速阈值电压失配补偿感测放大器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468393
T. Kawahara, T. Sakata, K. Itoh, Y. Kawajiri, T. Akiba, G. Kitsukawa, M. Aoki
{"title":"A High-Speed, Threshold-Voltage-Mismatch Compensation Sense Amplifier for Gb-scale DRAM Arrays","authors":"T. Kawahara, T. Sakata, K. Itoh, Y. Kawajiri, T. Akiba, G. Kitsukawa, M. Aoki","doi":"10.1109/ESSCIRC.1992.5468393","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468393","url":null,"abstract":"A high-speed, small-area DRAM sense amplifier with a threshold-voltage (VT) mismatch compensation function is proposed. This sense amplifier features a unique hierarchy data-line architecture with a direct sensing scheme which uses only nMOS transistors in the array, and a simple VT mismatch compensation circuitry which uses a pair of nMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of conventional common I/O CMOS sense amplifiers due to removing pMOS transistors from the array. The read-out time is improved to 35% that of conventional CMOS sense amplifiers, because of direct sensing and there is a 90% reduction in VT mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in future Gb-scale DRAM arrays.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126585083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Technology Independent Module Generator for CLA Adders 用于CLA加法器的技术独立模块生成器
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468190
W. Schardein, B. Weghaus, O. Maas, B. Hosticka, G. Troster
{"title":"A Technology Independent Module Generator for CLA Adders","authors":"W. Schardein, B. Weghaus, O. Maas, B. Hosticka, G. Troster","doi":"10.1109/ESSCIRC.1992.5468190","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468190","url":null,"abstract":"A technology independent generator for CLA adders in BiCMOS and CMOS is presented. It allows full automatic construction of fast parallel adders with arbitrary word length and device sizing. The automatic design cycle comprises the schematics and layout generation, netlist extraction from layout, and verification with pseudo random numbers. Also, the critical path is analyzed and the worst case delay time gained by simulation. An example of an 16 bit adder in a 0.8¿m BiCMOS and in a 2¿m CMOS technology is included.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"128 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123243493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Pragmatic Approach to Testing Mixed Analogue/Digital Circuits 一种实用的模拟/数字混合电路测试方法
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468414
G. Russell, G. Pettit
{"title":"A Pragmatic Approach to Testing Mixed Analogue/Digital Circuits","authors":"G. Russell, G. Pettit","doi":"10.1109/ESSCIRC.1992.5468414","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468414","url":null,"abstract":"The increased use of mixed analogue/digital circuits in VLSI designs has increased, enormously, the problems of testing these complex circuits. The problem is further compounded when these types of circuits are used in safety critical applications where there is a need to detect intermittent faults. The problem of intermittent fault detection has been solved to some extent for digital circuits, but remains a serious problem in analogue circuits. A pragmatic approach, called Residual Multiple Frequency Testing, is proposed for concurrent error detection in analogue circuits in which two pilot signals whose frequency lies, just outside, the operational bandwidth of the analogue circuit under test are continually monitored. Fluctuations in the output level of these pilot signals indicates a fault in the circuit. The format of the two rail error signal from the checking hardware is effectively compatible with that used in digital circuits.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog Circuit Implementation on CMOS Semi-Custom Arrays CMOS半自定义阵列的模拟电路实现
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468195
M. Declercq, P. Duchene, B. Goffart, M. Novak
{"title":"Analog Circuit Implementation on CMOS Semi-Custom Arrays","authors":"M. Declercq, P. Duchene, B. Goffart, M. Novak","doi":"10.1109/ESSCIRC.1992.5468195","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468195","url":null,"abstract":"The various requirements for implementing analog or mixed analog/digital circuits on semi-custom arrays are reviewed and discussed in relation with array architecture. Analog circuit techniques applicable to CMOS arrays are described, together with a detailed analysis of performance obtained at the building-block level and at the circuit level. An extended, high-performance array with a dedicated analog area and high-voltage output capability is finally presented.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130053606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Circuit and Architectural Optimization of Static Memories 静态存储器的电路与结构优化
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468385
V. Eisele, D. Schmitt-Landsiedel
{"title":"Circuit and Architectural Optimization of Static Memories","authors":"V. Eisele, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.1992.5468385","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468385","url":null,"abstract":"A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Sea-of-Gates Architecture Based on VLSI System Design Requirements 基于VLSI系统设计要求的海门架构
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468183
R.J.H. Koopman, H. Kerkhoff
{"title":"A Sea-of-Gates Architecture Based on VLSI System Design Requirements","authors":"R.J.H. Koopman, H. Kerkhoff","doi":"10.1109/ESSCIRC.1992.5468183","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468183","url":null,"abstract":"This paper presents a 1.0 ¿m double-metal layer CMOS sea-of-gates architecture based on requirements common to the entire VLSI application area instead of a specified field. These requirements include reduction of power consumption, transparent to design flow, be able to design circuits with densities limited only by the used technology, reduce the delay of critical paths and solve complex routing problems. The results of benchmark circuits will be presented to illustrate the functionality of the architecture.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimized Design For Test Techniques Applied to Embedded Mixed Mode Macros 嵌入式混合模式宏测试技术的优化设计
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468406
S. Allott, J. Raczkowycz
{"title":"Optimized Design For Test Techniques Applied to Embedded Mixed Mode Macros","authors":"S. Allott, J. Raczkowycz","doi":"10.1109/ESSCIRC.1992.5468406","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468406","url":null,"abstract":"In this paper we present an approach which aims to ease the testing problems associated with Mixed Mode ASICS, by concentrating on one particular area of concern, namely the testing of an embedded analogue to digital converter, an ADC. The method used outlines a novel concept of adapting the input pulse stimuli in such a way that the ADC can be tested using conventional analysis. An alternative to FFT analysis is proposed; the justification of which addresses the fundamental problems encountered in the testing of mixed mode circuits. A practical testing scheme is suggested that incorporates on chip hardware for the real time analysis of output data from the ADC.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129477294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-Level Design Strategies for Architectural Synthesis 建筑综合的高级设计策略
ESSCIRC '92: Eighteenth European Solid-State Circuits conference Pub Date : 1992-09-01 DOI: 10.1109/ESSCIRC.1992.5468448
N. Wehn, M. Payer
{"title":"High-Level Design Strategies for Architectural Synthesis","authors":"N. Wehn, M. Payer","doi":"10.1109/ESSCIRC.1992.5468448","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1992.5468448","url":null,"abstract":"In this paper we give an overview of state-of-the-art high-level design strategies. We introduce formal definitions of the terms high-level synthesis, behavioral synthesis, architectural synthesis, and register-transfer level synthesis. These definitions allow us to classify specification languages and synthesis systems. Furthermore, we discuss essential issues such as the impact of high-level synthesis on industrial design practice, modeling of the design space, the role of VHDL, and the hardware specification problem. To demonstrate different synthesis philosophies, we present the three synthesis systems CATHEDRAL, HIS, and CALLAS as typical examples. Each of these systems is intended for a different application domain, namely CATHEDRAL for digital signal processing algorithms, HIS for processor structures, and CALLAS for control-dominated designs.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115324326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信