A Technology Independent Module Generator for CLA Adders

Abstract

A technology independent generator for CLA adders in BiCMOS and CMOS is presented. It allows full automatic construction of fast parallel adders with arbitrary word length and device sizing. The automatic design cycle comprises the schematics and layout generation, netlist extraction from layout, and verification with pseudo random numbers. Also, the critical path is analyzed and the worst case delay time gained by simulation. An example of an 16 bit adder in a 0.8¿m BiCMOS and in a 2¿m CMOS technology is included.