Circuit and Architectural Optimization of Static Memories

Abstract

A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.