Optimized Design For Test Techniques Applied to Embedded Mixed Mode Macros

Abstract

In this paper we present an approach which aims to ease the testing problems associated with Mixed Mode ASICS, by concentrating on one particular area of concern, namely the testing of an embedded analogue to digital converter, an ADC. The method used outlines a novel concept of adapting the input pulse stimuli in such a way that the ADC can be tested using conventional analysis. An alternative to FFT analysis is proposed; the justification of which addresses the fundamental problems encountered in the testing of mixed mode circuits. A practical testing scheme is suggested that incorporates on chip hardware for the real time analysis of output data from the ADC.