W. Schardein, B. Weghaus, O. Maas, B. Hosticka, G. Troster
{"title":"用于CLA加法器的技术独立模块生成器","authors":"W. Schardein, B. Weghaus, O. Maas, B. Hosticka, G. Troster","doi":"10.1109/ESSCIRC.1992.5468190","DOIUrl":null,"url":null,"abstract":"A technology independent generator for CLA adders in BiCMOS and CMOS is presented. It allows full automatic construction of fast parallel adders with arbitrary word length and device sizing. The automatic design cycle comprises the schematics and layout generation, netlist extraction from layout, and verification with pseudo random numbers. Also, the critical path is analyzed and the worst case delay time gained by simulation. An example of an 16 bit adder in a 0.8¿m BiCMOS and in a 2¿m CMOS technology is included.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"128 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A Technology Independent Module Generator for CLA Adders\",\"authors\":\"W. Schardein, B. Weghaus, O. Maas, B. Hosticka, G. Troster\",\"doi\":\"10.1109/ESSCIRC.1992.5468190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A technology independent generator for CLA adders in BiCMOS and CMOS is presented. It allows full automatic construction of fast parallel adders with arbitrary word length and device sizing. The automatic design cycle comprises the schematics and layout generation, netlist extraction from layout, and verification with pseudo random numbers. Also, the critical path is analyzed and the worst case delay time gained by simulation. An example of an 16 bit adder in a 0.8¿m BiCMOS and in a 2¿m CMOS technology is included.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"128 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
提出了一种与技术无关的用于双mos和CMOS中CLA加法器的发生器。它允许全自动构建具有任意字长和设备大小的快速并行加法器。自动设计周期包括原理图和布局生成，从布局中提取网表，以及使用伪随机数进行验证。对关键路径进行了分析，并通过仿真得到了最坏情况下的延时时间。其中包括0.8 m BiCMOS和2 m CMOS技术中的16位加法器的示例。
A Technology Independent Module Generator for CLA Adders
A technology independent generator for CLA adders in BiCMOS and CMOS is presented. It allows full automatic construction of fast parallel adders with arbitrary word length and device sizing. The automatic design cycle comprises the schematics and layout generation, netlist extraction from layout, and verification with pseudo random numbers. Also, the critical path is analyzed and the worst case delay time gained by simulation. An example of an 16 bit adder in a 0.8¿m BiCMOS and in a 2¿m CMOS technology is included.
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