{"title":"基于VLSI系统设计要求的海门架构","authors":"R.J.H. Koopman, H. Kerkhoff","doi":"10.1109/ESSCIRC.1992.5468183","DOIUrl":null,"url":null,"abstract":"This paper presents a 1.0 ¿m double-metal layer CMOS sea-of-gates architecture based on requirements common to the entire VLSI application area instead of a specified field. These requirements include reduction of power consumption, transparent to design flow, be able to design circuits with densities limited only by the used technology, reduce the delay of critical paths and solve complex routing problems. The results of benchmark circuits will be presented to illustrate the functionality of the architecture.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Sea-of-Gates Architecture Based on VLSI System Design Requirements\",\"authors\":\"R.J.H. Koopman, H. Kerkhoff\",\"doi\":\"10.1109/ESSCIRC.1992.5468183\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 1.0 ¿m double-metal layer CMOS sea-of-gates architecture based on requirements common to the entire VLSI application area instead of a specified field. These requirements include reduction of power consumption, transparent to design flow, be able to design circuits with densities limited only by the used technology, reduce the delay of critical paths and solve complex routing problems. The results of benchmark circuits will be presented to illustrate the functionality of the architecture.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468183\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468183","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Sea-of-Gates Architecture Based on VLSI System Design Requirements
This paper presents a 1.0 ¿m double-metal layer CMOS sea-of-gates architecture based on requirements common to the entire VLSI application area instead of a specified field. These requirements include reduction of power consumption, transparent to design flow, be able to design circuits with densities limited only by the used technology, reduce the delay of critical paths and solve complex routing problems. The results of benchmark circuits will be presented to illustrate the functionality of the architecture.
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