Technology independent VLSI-Design using Bit Level self-timed circuits

Abstract

In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5¿m- and a 0,8¿m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5¿m) up to 100 MHz (0,8¿m) have been measured for self-timed asynchronous test circuits.