{"title":"采用位级自定时电路的技术独立vlsi设计","authors":"C. Heer, O. Aumann","doi":"10.1109/ESSCIRC.1992.5468165","DOIUrl":null,"url":null,"abstract":"In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5¿m- and a 0,8¿m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5¿m) up to 100 MHz (0,8¿m) have been measured for self-timed asynchronous test circuits.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Technology independent VLSI-Design using Bit Level self-timed circuits\",\"authors\":\"C. Heer, O. Aumann\",\"doi\":\"10.1109/ESSCIRC.1992.5468165\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5¿m- and a 0,8¿m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5¿m) up to 100 MHz (0,8¿m) have been measured for self-timed asynchronous test circuits.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468165\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Technology independent VLSI-Design using Bit Level self-timed circuits
In this paper self-timed circuits for synchronization at bit level are described. For a high functional throughput rate a circuit granularity of two full additions per handshake cycle will be proposed. Functionality of this concept is shown for a 1,5¿m- and a 0,8¿m-CMOS-technology. Technology migration is possible without any change of circuit design. Device performance enhancement is completely available for circuit speed-up. Clock frequencies of 35 MHz (1,5¿m) up to 100 MHz (0,8¿m) have been measured for self-timed asynchronous test circuits.
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