Analog Phase Measuring Circuit for Digital CMOS-ICS

Abstract

A circuit is described for use in digital systems. It allows to measure the phase of incoming asynchronous signals relative to the system clock. The reference of the asynchronous signal is the positive or negative slope. Its phase is measured with a resolution of 1/32 of a system clock cycle (50 .. 75 ns). Timing precision is better than 200 ps without any adjustments. One external capacitor is needed.