{"title":"一种双嵌套米勒补偿的CMOS低失真全差分功率放大器","authors":"S. Pernici, G. Nicollini, R. Castello","doi":"10.1109/ESSCIRC.1992.5468254","DOIUrl":null,"url":null,"abstract":"A four stages fully-differential amplifier that uses a double nested Miller compensated structure to lower harmonic distortion is presented. With a single 5V supply power dissipation is 10mW and THD is ¿83dB for a 6Vpp differential output signal at 10kHz and a load of 50¿. With 8¿ load and 10kHz, 4Vpp output signal, THD is ¿68dB. The chip area is 1000mils2 in a 1.5¿ n-well CMOS technology.","PeriodicalId":242379,"journal":{"name":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"52","resultStr":"{\"title\":\"A CMOS Low Distortion Fully Differential Power Amplifier With Double Nested Miller Compensation\",\"authors\":\"S. Pernici, G. Nicollini, R. Castello\",\"doi\":\"10.1109/ESSCIRC.1992.5468254\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A four stages fully-differential amplifier that uses a double nested Miller compensated structure to lower harmonic distortion is presented. With a single 5V supply power dissipation is 10mW and THD is ¿83dB for a 6Vpp differential output signal at 10kHz and a load of 50¿. With 8¿ load and 10kHz, 4Vpp output signal, THD is ¿68dB. The chip area is 1000mils2 in a 1.5¿ n-well CMOS technology.\",\"PeriodicalId\":242379,\"journal\":{\"name\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"volume\":\"162 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"52\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '92: Eighteenth European Solid-State Circuits conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1992.5468254\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '92: Eighteenth European Solid-State Circuits conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1992.5468254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS Low Distortion Fully Differential Power Amplifier With Double Nested Miller Compensation
A four stages fully-differential amplifier that uses a double nested Miller compensated structure to lower harmonic distortion is presented. With a single 5V supply power dissipation is 10mW and THD is ¿83dB for a 6Vpp differential output signal at 10kHz and a load of 50¿. With 8¿ load and 10kHz, 4Vpp output signal, THD is ¿68dB. The chip area is 1000mils2 in a 1.5¿ n-well CMOS technology.