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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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Transitive closure and graph component labeling on realistic processor arrays based on reconfigurable mesh network 基于可重构网格网络的真实处理器阵列传递闭包和图形组件标注
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139887
M. Maresca, P. Baglietto
{"title":"Transitive closure and graph component labeling on realistic processor arrays based on reconfigurable mesh network","authors":"M. Maresca, P. Baglietto","doi":"10.1109/ICCD.1991.139887","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139887","url":null,"abstract":"A O(log/sup 2/ n) complexity parallel algorithm is presented for graph component labeling and transitive closure on reconfigurable processor arrays. Although lower complexity algorithms for the same tasks on reconfigurable processor arrays have been proposed, the reconfigurable processor arrays supporting such algorithms have communication capabilities which are neither scalable nor suitable for VLSI implementation. On the contrary the algorithm presented is designed for a realistic class of reconfigurable processor arrays, called polymorphic processor arrays, which is both scalable and suitable for VLSI implementation.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116088317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An efficient pattern match architecture for production systems using content-addressable memory 使用内容可寻址内存的生产系统的有效模式匹配体系结构
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139923
C. Dou, Shao-Ming Wu
{"title":"An efficient pattern match architecture for production systems using content-addressable memory","authors":"C. Dou, Shao-Ming Wu","doi":"10.1109/ICCD.1991.139923","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139923","url":null,"abstract":"A novel and efficient content-addressable pattern match architecture (CAPMA) is proposed to speed up the execution time of the match process of a production system. CAPMA compiles the left-hand side (LHS) of each production into an efficient symbolic form, and creates an effective symbolic accessing mechanism based on a two-level content-addressable memory (CAM) structure for computing the conflict set. Preliminary (performance estimation) shows that averaging 2500 match clocks of CAM are needed for each match cycle. That is, CAPMA can perform approximately 8000 match cycles per second using 20 MHz CAMs.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Random testability of redundant circuits 冗余电路的随机可测试性
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139936
A. Krasniewski, A. Albicki
{"title":"Random testability of redundant circuits","authors":"A. Krasniewski, A. Albicki","doi":"10.1109/ICCD.1991.139936","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139936","url":null,"abstract":"It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network is formulated.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a self-testing checker for Borden code Borden代码的自检检查器设计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139978
S. Piestrak
{"title":"Design of a self-testing checker for Borden code","authors":"S. Piestrak","doi":"10.1109/ICCD.1991.139978","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139978","url":null,"abstract":"A Borden code is an optimal code capable of detecting t-unidirectional errors. A new self-testing checker (STC) for Borden code is proposed. It is built of two blocks: a self-testing code-disjoint translator of the Borden code onto the one-out-of-r code (r>or=4) and a well-known STC for the one-out-of-r code. The translator is built of two multi-output threshold circuits and a NOT-AND-OR circuit. The new checker has significantly better performance than the STC for Borden code proposed previously by N. K. Jha (1989). Its highly regular modular structure and easy testability make it particularly attractive for a VLSI implementation.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123788922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design methodology for a MIPS compatible embedded control processor MIPS兼容嵌入式控制处理器的设计方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139909
Raymond Peck, Jay Patel
{"title":"Design methodology for a MIPS compatible embedded control processor","authors":"Raymond Peck, Jay Patel","doi":"10.1109/ICCD.1991.139909","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139909","url":null,"abstract":"The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131477725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nimbus: An integrated display chip 光轮:集成显示芯片
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139993
B. Locanthi, R. McLellan
{"title":"Nimbus: An integrated display chip","authors":"B. Locanthi, R. McLellan","doi":"10.1109/ICCD.1991.139993","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139993","url":null,"abstract":"With SRAM technology delivering more than a million bits per chip, it is now feasible to integrate display memory with display control. The circuit described contains a two-port SRAM array, one port being serial access combined with duty cycle modulation for gray-scale display on LCDs. The memory array itself is synchronous with the processor port, providing low-latency, high-bandwidth access for image manipulation.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129600457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal clocking of circular pipelines 圆形管道的最佳时钟
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139992
K. Sakallah, T. Mudge, Timothy M. Burks, E. Davidson
{"title":"Optimal clocking of circular pipelines","authors":"K. Sakallah, T. Mudge, Timothy M. Burks, E. Davidson","doi":"10.1109/ICCD.1991.139992","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139992","url":null,"abstract":"A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134381043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High-performance VLSI processor for robot inverse dynamics computation 机器人逆动力学计算的高性能VLSI处理器
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139984
Somchai Kittichaikoonkit, M. Kameyama, T. Higuchi
{"title":"High-performance VLSI processor for robot inverse dynamics computation","authors":"Somchai Kittichaikoonkit, M. Kameyama, T. Higuchi","doi":"10.1109/ICCD.1991.139984","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139984","url":null,"abstract":"A VLSI-oriented matrix multiply-addition processor (MMP) is proposed for minimum-delay-time inverse dynamics computation on a linear array structure. It is shown that the delay time of the inverse dynamics computation becomes minimum based on the concept of the odd-even alternative computation. The MMP architecture is systematically designed by using two types of data-dependence graphs of the odd-even alternative computation. It is demonstrated by the layout evaluation that the MMP can be easily implemented in a single chip using the current VLSI technology (e.g. 1 mu m CMOS). The performance with regard to the delay time is higher than for previously reported architectures.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132213007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Stafan algorithms for MOS circuits MOS电路的Stafan算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139844
Joan Villoldo, P. Agrawal, V. Agrawal
{"title":"Stafan algorithms for MOS circuits","authors":"Joan Villoldo, P. Agrawal, V. Agrawal","doi":"10.1109/ICCD.1991.139844","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139844","url":null,"abstract":"Novel models and algorithms for MOS transmission gates, buses and functional memories for use in statistical fault analysis (Stafan) are described. A bus is modeled as a multiple input multiplexer with feedback to account for its memory state. A CMOS transmission gate, modeled as a unidirectional device, always feeds into a bus that processes the high impedance state. Novel algorithms are devised to compute input observabilities of functional memory blocks. A novel implementation of Stafan algorithms is described for the MARS hardware accelerator environment. MARs is run in the true-value simulation mode and sends signal changes for all lines through a Unix pipe to the Stafan process running on a SUN workstation. The Stafan process computes controllabilities, observabilities, detection probabilities, and fault coverage. MARS and Stafan thus run as a pipeline. Results on several CMOS circuits are obtained and compared with those obtained from a concurrent fault simulator.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114773739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A GaAs receiver module for optoelectronic computing and interconnection 一种用于光电计算和互连的GaAs接收器模块
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139956
Joongho Choi, B. Sheu
{"title":"A GaAs receiver module for optoelectronic computing and interconnection","authors":"Joongho Choi, B. Sheu","doi":"10.1109/ICCD.1991.139956","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139956","url":null,"abstract":"A GaAs gigahertz optical receiver module was designed and fabricated through a MESFET technology. Design techniques were used to increase the bandwidth of the receiver circuit. Basic digital circuits were also fabricated to extract technology parameters and to provide information for higher levels of integration. This receiver and the associated laser diode based transmitter are suitable for integrated optoelectronic signal processing and optical neurocomputing.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133853591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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