圆形管道的最佳时钟

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139992

K. Sakallah, T. Mudge, Timothy M. Burks, E. Davidson

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引用次数: 8

摘要

提出了一种圆形管道的时序模型，用于计算电路延迟和时钟偏差的最小周期时间。该模型考虑了短路径和长路径延迟、时钟偏差的影响，以及锁存器和触发器作为同步元件的使用。描述了求单相时钟和一类受限制的多相时钟最小周期时间的算法的制定和实现。

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Optimal clocking of circular pipelines

A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described.<>

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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