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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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Dual global flow 双全球流
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139842
R. Damiano, Len Berman
{"title":"Dual global flow","authors":"R. Damiano, Len Berman","doi":"10.1109/ICCD.1991.139842","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139842","url":null,"abstract":"A combinatorial logic optimization is described. The optimization is (in some sense) a dual of earlier global flow optimizations. The optimization leaves the function carried by each signal in the circuit unchanged and thus avoids expensive recomputation of don't care information. The results of experiments performed to evaluate this optimization are also described.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121374470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A built-in self-testing approach for minimizing hardware overhead 用于最小化硬件开销的内置自我测试方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139898
S. Chiu, C. Papachristou
{"title":"A built-in self-testing approach for minimizing hardware overhead","authors":"S. Chiu, C. Papachristou","doi":"10.1109/ICCD.1991.139898","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139898","url":null,"abstract":"A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"223 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127297270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A layout compaction algorithm with multiple grid constraints 具有多个网格约束的布局压缩算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139837
Jin-fuw Lee
{"title":"A layout compaction algorithm with multiple grid constraints","authors":"Jin-fuw Lee","doi":"10.1109/ICCD.1991.139837","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139837","url":null,"abstract":"As the chip density grows, wiring circuits on a VLSI chip becomes hard. It is then important to leave feed-through channels in the layouts of cells and macros. One strategy to achieve this goal is to keep wires on their respective wiring grids. This requirement presents a new constraint to the compaction problem of cells and macros. A new efficient algorithm is proposed to solve such a compaction problem on multiple grids. The worst-case time complexity of the algorithm is O((M+1) ( mod V mod + mod E mod )). The algorithm has been implemented in a compactor and applied to the layout designs for both microprocessor chips and ASIC chips.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125268602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fine grain architecture for parallel fault simulation 并行断层模拟的细粒度结构
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139846
J. Trotter, R. Evans
{"title":"A fine grain architecture for parallel fault simulation","authors":"J. Trotter, R. Evans","doi":"10.1109/ICCD.1991.139846","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139846","url":null,"abstract":"An architecture is presented for performing event-driven logic simulation using either unit or zero gate delay models. The architecture is based on a fine grain logic gate evaluation element which can simulate a single gate in a circuit. These simple elements can be implemented using VLSI and many such elements make up the simulation architecture. Each gate evaluation element can match a node identifier transmitted on a bus allowing the architecture to search fanout lists in one cycle. The gate evaluation element is designed with additional circuitry allowing it to save or restore the complete state of the machine in one cycle so it can support fault simulation using the concurrent and differential fault simulation algorithms.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116085859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An effective analog approach to Steiner routing 一种有效的斯坦纳路由模拟方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139873
A. Kahng
{"title":"An effective analog approach to Steiner routing","authors":"A. Kahng","doi":"10.1109/ICCD.1991.139873","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139873","url":null,"abstract":"Construction of a minimum rectilinear Steiner tree (MRST) is a fundamental problem in the physical design of VLSI circuits. The problem is NP-complete, and numerous heuristics have been proposed. A novel analog approach is proposed which intuitively shrinks a bubble around the pins of the signal net until a Steiner tree topology is induced. The method easily maps to parallel neural-style architectures, as well as to fairly generic two-dimensional processor arrays. Extensive simulation results show better performance than virtually all existing MRST approaches. The result is a rare instance where an analog heuristic for an NP-complete problem outperforms existing combinatorial methods, both in time complexity and in average-case performance.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128261316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implicit manipulation of equivalence classes using binary decision diagrams 使用二元决策图的等价类的隐式操作
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139995
Bill Lin, A. Newton
{"title":"Implicit manipulation of equivalence classes using binary decision diagrams","authors":"Bill Lin, A. Newton","doi":"10.1109/ICCD.1991.139995","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139995","url":null,"abstract":"A novel representation called an equivalence class characterization function is defined. It can implicitly represent all equivalence classes with a compact characteristic function that will have at most n outputs. Using binary decision diagrams (BDDs) and the concept of the equivalence class characterization function, very large problem instances can be represented. For manipulating equivalence classes efficiently, a Boolean operator called a compatible projection operator is proposed. Conceptually, the compatible projection operator is used to uniquely select a single element from each equivalence class to characterize the class. In manipulating equivalence classes, the compatible projection operator is used to implicitly derive an encoding function from the equivalence relation that encodes the equivalence class information symbolically. An efficient implementation is described based on BDDs that is applied to very large problem instances.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Decomposed arbiters for large crossbars with multi-queue input buffers 具有多队列输入缓冲区的大型交叉栏的分解仲裁器
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139888
Hsin-Chou Chi, Y. Tamir
{"title":"Decomposed arbiters for large crossbars with multi-queue input buffers","authors":"Hsin-Chou Chi, Y. Tamir","doi":"10.1109/ICCD.1991.139888","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139888","url":null,"abstract":"Crossbars are key components of communication switches used to construct multiprocessor interconnection networks. For a fixed number of nodes, larger crossbars result in reduced probability of conflicts and allow packets to traverse the network in fewer hops. However, increasing the size of the crossbar also increases the delay of the arbiter used to resolve conflicting requests. The increased arbitration delay can lead to overall poor network performance. The impact of the increased arbitration delay can be mitigated by decomposing the arbitration process into multiple steps, such that some requests can be granted before the arbitration of the entire crossbar is complete. The design of such decomposed arbiters for larger crossbars is discussed. The focus is on crossbars with multi-queue buffers at their inputs. Such buffers have been shown to provide significantly higher performance than conventional FIFO buffers.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129635096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
DesignFab: a methodology for ULSI microprocessor design DesignFab:一种用于ULSI微处理器设计的方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139864
Moshe Shahaf
{"title":"DesignFab: a methodology for ULSI microprocessor design","authors":"Moshe Shahaf","doi":"10.1109/ICCD.1991.139864","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139864","url":null,"abstract":"A novel design methodology and CAD tool set are described and successfully used in the design of a 100 MIPS superscalar ULSI microprocessor with DSP capabilities for embedded applications. The design process starts with the architecture definition, and a high level behavioral model is written. This model is then synthesized into a gate level description which is translated into a description to be used in the actual layout.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Methods and algorithms for converting IC designs between incompatible design systems 在不兼容的设计系统之间转换IC设计的方法和算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139838
E. Pajarre, T. Ritoniemi, H. Tenhunen
{"title":"Methods and algorithms for converting IC designs between incompatible design systems","authors":"E. Pajarre, T. Ritoniemi, H. Tenhunen","doi":"10.1109/ICCD.1991.139838","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139838","url":null,"abstract":"Methods and algorithms are described for converting designs from a geometrical database design system to a design system which is based on basic electrical objects. The feasibility of these algorithms is demonstrated using GDS II and L language as examples. The performance of the system is such that it can be used in design verification by converting mask layouts to a format suitable for simulation.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131846297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accessibility analysis on data flow graph: an approach to design for testability 数据流图的可访问性分析:一种可测试性设计方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139948
Chung-Hsing Chen, Chienwen Wu, D. Saab
{"title":"Accessibility analysis on data flow graph: an approach to design for testability","authors":"Chung-Hsing Chen, Chienwen Wu, D. Saab","doi":"10.1109/ICCD.1991.139948","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139948","url":null,"abstract":"Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nodes are accessible. A simple modification to the DFG that increases accessibility is presented.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132932318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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