发布求助
文献互助 智能选刊 最新文献

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

筛选
英文 中文
Performance-driven global routing for cell based ICs 基于单元的集成电路的性能驱动的全局路由
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139874
J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, Chak-Kuen Wong
{"title":"Performance-driven global routing for cell based ICs","authors":"J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, Chak-Kuen Wong","doi":"10.1109/ICCD.1991.139874","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139874","url":null,"abstract":"Advances in VLSI technology and the increased complexity of circuit designs cause performance to become an increasingly important constraint for layout. The issue of delay optimization during the global routing phase is addressed. This problem is formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics is presented. This approach has very good empirical performance with respect to total wirelength, and can be smoothly tuned between the competing requirements of minimum delay and minimum total netlength, as confirmed by extensive computational results which confirm this. Extensions can be made to the graph and Steiner versions of the problem, and a number of open problems are described.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130945780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Gigascale integration (GIS) in the 21st century 21世纪的Gigascale integrated (GIS)
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139940
J. Meindl
{"title":"Gigascale integration (GIS) in the 21st century","authors":"J. Meindl","doi":"10.1109/ICCD.1991.139940","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139940","url":null,"abstract":"Summary form only given. Opportunities for incorporation of more than one billion transistors and associated interconnections with a single silicon chip or for gigascale integration (GSI) are governed by a hierarchy of limits whose levels can be codified as fundamental, material, device, circuit, and system. Each level of this hierarchy includes both theoretical and practical limits. Theoretical limits are determined solely by physical principles. Practical limits are strongly influenced by manufacturing technology and markets and can be described in terms of the minimum feature size, the square root of die area, and the packing efficiency (defined as the number of transistors or components per minimum feature area). The singular metric that reveals the efficacy of a technology for GSI is the chip performance index (CPI) defined as the quotient of the number of transistors per chip (N) and the associated power-delay product (Pt/sub d/) or CPI=N/Pt/sub d/. The CPI increased by about 10/sup 13/ from 1960 to 1990 and is projected to increase by another factor of 10/sup 6/ from 1990 to 2020.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117185918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
BioSCAN: a VLSI-based system for biosequence analysis BioSCAN:基于vlsi的生物序列分析系统
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139959
C. T. White, Raj K. Singh, Peter B. Reintjes, J. Lampe, B. W. Erickson, W. Dettloff, V. Chi, S. Altschul
{"title":"BioSCAN: a VLSI-based system for biosequence analysis","authors":"C. T. White, Raj K. Singh, Peter B. Reintjes, J. Lampe, B. W. Erickson, W. Dettloff, V. Chi, S. Altschul","doi":"10.1109/ICCD.1991.139959","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139959","url":null,"abstract":"A special-purpose computer system has been designed to accelerate scanning large databases of DNA and protein sequences (biosequences) for patterns of interest. The system consists of a custom-designed circuit board installed in a host workstation and associated software. The board features a variable number of identical full-custom ASICs. Each biological sequence comparative analysis node. (BioSCAN) ASIC, in turn, features a large one-dimensional systolic array of identical processing elements (PEs). The BioSCAN system scans approximately two million database elements per second. For typical problems this results in a 1000-fold speedup over current workstations.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
High performance packaged electronics for the IBM ES9000 mainframe 用于IBM ES9000大型机的高性能封装电子产品
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139967
A. E. Barish, J. Eckhardt, M. Mayo, W. A. Svarczkopf, S. Gaur, R. Tummala
{"title":"High performance packaged electronics for the IBM ES9000 mainframe","authors":"A. E. Barish, J. Eckhardt, M. Mayo, W. A. Svarczkopf, S. Gaur, R. Tummala","doi":"10.1109/ICCD.1991.139967","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139967","url":null,"abstract":"An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129030619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Operation method in fuzzy set operation processor 模糊集运算处理器中的运算方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139921
A. Katsumata, Hidekazu Tokunaga, S. Yasunobu
{"title":"Operation method in fuzzy set operation processor","authors":"A. Katsumata, Hidekazu Tokunaga, S. Yasunobu","doi":"10.1109/ICCD.1991.139921","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139921","url":null,"abstract":"A VLSI for diverse fuzzy set operations (FSP: fuzzy set processor) uses a single instruction multiple data stream (SIMD) architecture that is composed of four basic operation units and a variable microprogram control circuit. Speed increases of 50 times over a RISC-type CPU are possible when executing fuzzy set operations using a 16 basic operation unit (four processor) SIMD architecture.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132843946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast differential fault simulation by dynamic fault ordering 基于动态故障排序的快速微分故障仿真
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139845
G. Cabodi, S. Gai, M. Reorda
{"title":"Fast differential fault simulation by dynamic fault ordering","authors":"G. Cabodi, S. Gai, M. Reorda","doi":"10.1109/ICCD.1991.139845","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139845","url":null,"abstract":"A technique that makes it possible to significantly improve the effectiveness of the differential algorithm for the fault simulation of synchronous sequential circuits is presented. The approach is based on dynamically reordering the fault list before the simulation of each input pattern: faults not yet detected are grouped according to a strategy aiming at minimizing the status differences between successive faults. In such a way the activity to be processed while computing each faulty circuit is minimized at a quite low computational cost. Experimental results are provided showing the effectiveness of the proposed method.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A fast division algorithm for VLSI VLSI快速除法算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139973
N. Burgess
{"title":"A fast division algorithm for VLSI","authors":"N. Burgess","doi":"10.1109/ICCD.1991.139973","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139973","url":null,"abstract":"A novel and fast method for VLSI division is presented. The method is based on Svoboda's algorithm and uses the radix-2 signed-digit number system to give a divider in which quotient bit selection is a function of the two most significant digits of the current partial remainder. An n-bit divider produces an n-bit quotient in redundant form in 3n gate delays using n(n-1) controlled full add/subtract circuits. Operand pre-scaling necessary for the algorithm is accomplished by a single subtraction.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123691373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
IBM AS/400 processor technology IBM AS/400处理器技术
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139944
D. Cox, Charles L. Johnson, B. G. Rudolph, D. Siljenberg, R. R. Williams
{"title":"IBM AS/400 processor technology","authors":"D. Cox, Charles L. Johnson, B. G. Rudolph, D. Siljenberg, R. R. Williams","doi":"10.1109/ICCD.1991.139944","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139944","url":null,"abstract":"The architecture of the IBM AS/400 processor has unique silicon performance and density requirements which are addressed with 12.7 mm CMOS ASIC chips utilizing 0.8 mu m lithography and 0.5 mu m channel lengths. The I/O performance and high simultaneous switch requirements for the processor are resolved with a high performance, ceramic, multi-chip module and digital slope controlled off-chip drivers. Four phase clocks are implemented to meet functional requirements. The system clock skews were minimized through a distributed phase-lock-loop and an automated procedure to balance clocks on the logic chips. The larger processor to I/O device distance requirements led to the implementation of a serial fiber optic link as the I/O bus extender. The underlying requirements for all of the technologies utilized in the AS/400 were high quality and high productivity.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114195597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
IBM AS/400 processor architecture and design methodology IBM AS/400处理器体系结构和设计方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139942
Quentin G. Schmierer, Andrew H. Wottreng
{"title":"IBM AS/400 processor architecture and design methodology","authors":"Quentin G. Schmierer, Andrew H. Wottreng","doi":"10.1109/ICCD.1991.139942","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139942","url":null,"abstract":"The IBM AS/400 is a family of general purpose mid-range computers specifically designed to run commercial business applications and transaction processing in batch and interactive environments. The April, 1991 announcement is the second generation of the system. It provides a 2.7 times performance improvement over its predecessor. Architectural support for multiprocessors is also part of the product. Achieving this performance improvement required significant changes to the processor architecture, chip technologies and operating system hardware. The architecture and design methodology used in the IBM AS/400 processor are briefly described. The processor chip designs made extensive use of high level hardware description languages and logic synthesis. Each design group was responsible for defining its design in VHDL and converting the design into logic using logic synthesis. The designer's experiences with these new methods are highlighted.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125276886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A tag coprocessor architecture for symbolic languages 符号语言的标签协处理器架构
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139922
V. Fuentes-Sánchez, P. Cheung
{"title":"A tag coprocessor architecture for symbolic languages","authors":"V. Fuentes-Sánchez, P. Cheung","doi":"10.1109/ICCD.1991.139922","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139922","url":null,"abstract":"A novel architecture is presented for the efficient execution of symbolic languages on conventional von Neumann, register-based machines. Unlike other symbolic processing architectures, this is based on a tag coprocessor (TC) which is designed to work in parallel with a conventional RISC CPU such as the MIPS R3000. The TC performs almost all the tag manipulation operations independently of the CPU. It can also perform stack height checking, range checking and loop control. This design significantly enhances the execution speed of symbolic languages such as Lisp and Prolog on a RISC processor, yet all existing software for the CPU without the TC will work with minimal modification. The simplicity of the TC architecture provides a cost-effective way of designing systems specifically for artificial intelligence applications.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"15 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121246797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信