D. Cox, Charles L. Johnson, B. G. Rudolph, D. Siljenberg, R. R. Williams
{"title":"IBM AS/400 processor technology","authors":"D. Cox, Charles L. Johnson, B. G. Rudolph, D. Siljenberg, R. R. Williams","doi":"10.1109/ICCD.1991.139944","DOIUrl":null,"url":null,"abstract":"The architecture of the IBM AS/400 processor has unique silicon performance and density requirements which are addressed with 12.7 mm CMOS ASIC chips utilizing 0.8 mu m lithography and 0.5 mu m channel lengths. The I/O performance and high simultaneous switch requirements for the processor are resolved with a high performance, ceramic, multi-chip module and digital slope controlled off-chip drivers. Four phase clocks are implemented to meet functional requirements. The system clock skews were minimized through a distributed phase-lock-loop and an automated procedure to balance clocks on the logic chips. The larger processor to I/O device distance requirements led to the implementation of a serial fiber optic link as the I/O bus extender. The underlying requirements for all of the technologies utilized in the AS/400 were high quality and high productivity.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The architecture of the IBM AS/400 processor has unique silicon performance and density requirements which are addressed with 12.7 mm CMOS ASIC chips utilizing 0.8 mu m lithography and 0.5 mu m channel lengths. The I/O performance and high simultaneous switch requirements for the processor are resolved with a high performance, ceramic, multi-chip module and digital slope controlled off-chip drivers. Four phase clocks are implemented to meet functional requirements. The system clock skews were minimized through a distributed phase-lock-loop and an automated procedure to balance clocks on the logic chips. The larger processor to I/O device distance requirements led to the implementation of a serial fiber optic link as the I/O bus extender. The underlying requirements for all of the technologies utilized in the AS/400 were high quality and high productivity.<>
IBM AS/400处理器的架构具有独特的硅性能和密度要求,采用0.8 μ m光刻和0.5 μ m通道长度的12.7 mm CMOS ASIC芯片可以解决这些问题。处理器的I/O性能和高同时开关要求通过高性能,陶瓷,多芯片模块和数字斜率控制的片外驱动器解决。实现了四个相位时钟以满足功能需求。通过一个分布式锁相环和一个自动程序来平衡逻辑芯片上的时钟,系统时钟偏差被最小化。较大的处理器到I/O设备的距离要求导致了串行光纤链路作为I/O总线扩展器的实现。AS/400中使用的所有技术的基本要求是高质量和高生产率。