A. E. Barish, J. Eckhardt, M. Mayo, W. A. Svarczkopf, S. Gaur, R. Tummala
{"title":"High performance packaged electronics for the IBM ES9000 mainframe","authors":"A. E. Barish, J. Eckhardt, M. Mayo, W. A. Svarczkopf, S. Gaur, R. Tummala","doi":"10.1109/ICCD.1991.139967","DOIUrl":null,"url":null,"abstract":"An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.<>