发布求助
文献互助 智能选刊 最新文献

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

筛选
英文 中文
Testing of analog neural array-processor chips 模拟神经阵列处理器芯片的测试
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139859
Wen-Jay Hsu, B. Sheu, S. Gowda
{"title":"Testing of analog neural array-processor chips","authors":"Wen-Jay Hsu, B. Sheu, S. Gowda","doi":"10.1109/ICCD.1991.139859","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139859","url":null,"abstract":"A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"212 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116113243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Synthesis of delay-insensitive circuits by refinement into atomic threads 通过细化到原子线程来合成延迟不敏感电路
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139877
H. F. Li, S. Leung, P. N. Lam
{"title":"Synthesis of delay-insensitive circuits by refinement into atomic threads","authors":"H. F. Li, S. Leung, P. N. Lam","doi":"10.1109/ICCD.1991.139877","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139877","url":null,"abstract":"An optimization strategy based on time-sharing was previously proposed by the authors (1991). A process is decomposed into threads and the technique of time-sharing is applied in the synthesis of each thread and the synchronization requirements among threads. This study presents an extension of the methodology to nondeterminate processes. The synchronization requirements among threads include the passing of choice information as well as the causal relations between events from different threads. Substantial reduction in circuitry for realizing the synchronization requirements is observed if the choice states of threads are atomic (necessarily reached) and all the occurrences of an action belong to a thread. A theory on extracting threads that have the above properties and on synthesizing the synchronization requirements among threads is outlined.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123711883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A comparison of redundant CORDIC rotation engines 冗余CORDIC旋转发动机的比较
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139972
J. Harding, T. Lang, Jeong-A Lee
{"title":"A comparison of redundant CORDIC rotation engines","authors":"J. Harding, T. Lang, Jeong-A Lee","doi":"10.1109/ICCD.1991.139972","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139972","url":null,"abstract":"The CMOS implementation of two high performance rotation processors using redundant CORDIC are reviewed and compared. One of the designs uses a variable scaling factor while the other is with constant scaling. The latter also incorporates some radix-4 CORDIC stages. Characteristics for 1.2 mu m CMOS implementations are given.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Indentification of viable paths using binary decision diagrams 使用二元决策图确定可行路径
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139991
Yun-Cheng Ju, R. Saleh
{"title":"Indentification of viable paths using binary decision diagrams","authors":"Yun-Cheng Ju, R. Saleh","doi":"10.1109/ICCD.1991.139991","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139991","url":null,"abstract":"An efficient algorithm for the indentification of viable paths in a combinational logic circuit using binary decision diagrams is described. The viable paths are justified by generating and resolving logic and delay constraints along the critical path based on the stable times and stable values of the side inputs. Results of the analysis, using the ISCAS combinational benchmark circuits, indicate that most of the circuits can be analyzed in a few CPU-seconds.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122075638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation F-RISC/I:采用GaAs (H) MESFET实现的快速精简指令集计算机
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139901
C. K. Tien, C. C. Poon, H. Greub, J. McDonald
{"title":"F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation","authors":"C. K. Tien, C. C. Poon, H. Greub, J. McDonald","doi":"10.1109/ICCD.1991.139901","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139901","url":null,"abstract":"F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116726435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fine-line printed circuit board for high-performance computer design 用于高性能计算机的细线印刷电路板设计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139951
C. Huang, J. Willis, T. Schmitt
{"title":"Fine-line printed circuit board for high-performance computer design","authors":"C. Huang, J. Willis, T. Schmitt","doi":"10.1109/ICCD.1991.139951","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139951","url":null,"abstract":"Properties of a new fine-line printed circuit board which are critical in the design of computer systems based on GaAs, 100 K and 10 K logic families, are characterized. The new PCB technology permits trace widths as fine as 0.002 in. on the inner layers of multilayer boards. While facilitating higher package density and controlled impedance interconnects with higher characteristic impedance (Z/sub 0/), the technology opens questions of thermal reliability, ohmic heating, and noise margin. Cross-validating analytic and laboratory analysis is used to investigate each of these issues. Provided that several key issues are addressed during design, this report supports the use of 0.002 in. technology in high-performance computer systems.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration 一种用于动态处理器重构的自适应硬件机器架构和编译器
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139928
P. Athanas, H. Silverman
{"title":"An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration","authors":"P. Athanas, H. Silverman","doi":"10.1109/ICCD.1991.139928","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139928","url":null,"abstract":"Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to a user's program. A method is presented for improving the performance of many computationally intensive tasks by extracting information at compile-time to synthesize new operations that augment the functionality of a core processor. The newly synthesized operations are targeted to RAM-based reconfigurable logic located within the processor. A proof-of-concept system called PLADO, consisting of a C configuration compiler and a hardware platform, is presented. Computation and performance results confirm the concept viability, and demonstrate significant speed-up.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"s3-16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Fast capacitance extraction of general three-dimensional structures 一般三维结构的快速电容提取
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139952
K. Nabors, S. Kim, Jacob K. White, S. Senturia
{"title":"Fast capacitance extraction of general three-dimensional structures","authors":"K. Nabors, S. Kim, Jacob K. White, S. Senturia","doi":"10.1109/ICCD.1991.139952","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139952","url":null,"abstract":"Several improvements to the multipole-accelerated 3-D capacitance extraction program previously described are presented. A new adaptive multipole algorithm is given, and a preconditioning strategy for accelerated iterative method convergence is described. Results using these algorithms to compute the capacitance of general three-dimensional structures are presented, and they demonstrate that the modified approach is nearly as accurate as the more standard direct factorization algorithm, and can be as much as two orders of magnitude faster.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131235454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 193
New implementations, tools, and experiments for decreasing self-checking PLAs area overhead 减少自检pla面积开销的新实现、工具和实验
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139897
M. Nicolaidis, M. Boudjit
{"title":"New implementations, tools, and experiments for decreasing self-checking PLAs area overhead","authors":"M. Nicolaidis, M. Boudjit","doi":"10.1109/ICCD.1991.139897","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139897","url":null,"abstract":"Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger code encoded programmable logic arrays (PLAs) result in 46.9% average area overhead. In order to decrease this overhead, some other self-checking PLA implementations based on the Berger code are proposed. The tool allowing the generation of the conventional Berger code coded PLAs is modified to perform the new implementations. Experiments on the same set of PLAs show that the new implementations reduce the average area overhead from 46.9% to 20.1%.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126046750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Implementation-independent model of an instruction set architecture using VHDL 用VHDL实现的指令集体系结构独立模型
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139865
M. H. Salinas, Barry W. Johnson, J. Aylor
{"title":"Implementation-independent model of an instruction set architecture using VHDL","authors":"M. H. Salinas, Barry W. Johnson, J. Aylor","doi":"10.1109/ICCD.1991.139865","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139865","url":null,"abstract":"A novel methodology is presented which allows the creation of implementation-independent functional models of systems. The methodology uses the VHSIC (very high speed integrated circuit) hardware description language (VHDL) which leads to the possibility of creating a unified design environment supporting system modeling at various stages of the design process. The motivation for the methodology was to assist in the analysis and specification of the WM computer architecture. An implementation-independent model of the WM architecture is provided which is intended as a first step in the development of an implementation. Additionally, architectural performance measures can be extracted from simulations using the model. The model can also serve as an architectural specification for the WM computer.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129976412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信