New implementations, tools, and experiments for decreasing self-checking PLAs area overhead

Abstract

Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger code encoded programmable logic arrays (PLAs) result in 46.9% average area overhead. In order to decrease this overhead, some other self-checking PLA implementations based on the Berger code are proposed. The tool allowing the generation of the conventional Berger code coded PLAs is modified to perform the new implementations. Experiments on the same set of PLAs show that the new implementations reduce the average area overhead from 46.9% to 20.1%.<>