Testing of analog neural array-processor chips

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139859

Wen-Jay Hsu, B. Sheu, S. Gowda

引用次数: 5

Abstract

A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.<>

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模拟神经阵列处理器芯片的测试

提出了一种测试模拟阵列处理器神经芯片的系统方法。描述了模拟神经芯片的独特测试问题，并讨论了有效的解决方案。基于分层方法，可以系统地解决模拟阵列处理器神经芯片的测试问题。介绍了用2 μ m CMOS工艺制作的可编程模拟神经芯片的测试结果。这些芯片包含25个神经元和1600个突触。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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