F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139901

C. K. Tien, C. C. Poon, H. Greub, J. McDonald

引用次数: 4

Abstract

F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si.<>

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F-RISC/I:采用GaAs (H) MESFET实现的快速精简指令集计算机

F-RISC/I是一款单片砷化镓微处理器，具有七级流水线，采用SBFL标准单元。它的目标时钟频率为400 MHz, CPI为1.45。讨论了GaAs技术对F-RISC/I的系统架构、CPU架构、电路级优化、实现、性能和测试的影响。研究了GaAs的技术环境，并与Si的技术环境进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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