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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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An optimal algorithm for spiral floorplan designs 螺旋平面设计的最优算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139962
Cheng-Hsi Chen, I. Tollis
{"title":"An optimal algorithm for spiral floorplan designs","authors":"Cheng-Hsi Chen, I. Tollis","doi":"10.1109/ICCD.1991.139962","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139962","url":null,"abstract":"An improved algorithm for solving the area optimization problem of spiral floorplans is presented. Each of the five basic rectangles of a spiral floorplan have O(n) implementations. The algorithm takes O(n/sup 2/logn) time, and requires O(n/sup 2/) space to solve the area optimization problem. The best previously known algorithm solved the problem in O(n/sup 3/logn) time and O(n/sup 3/) space.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Technologies for rapid prototyping of multi-chip modules 多芯片模块快速成型技术
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139980
R. Miracky, T. Bishop, C. Galanakis, H. Hashemi, T. Hirsch, S. Madere, Heinrich G. Müller, T. Rudwick, L. Smith, S. Sommerfeldt, B. Weigler
{"title":"Technologies for rapid prototyping of multi-chip modules","authors":"R. Miracky, T. Bishop, C. Galanakis, H. Hashemi, T. Hirsch, S. Madere, Heinrich G. Müller, T. Rudwick, L. Smith, S. Sommerfeldt, B. Weigler","doi":"10.1109/ICCD.1991.139980","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139980","url":null,"abstract":"Component technologies are described to be used in the maskless customization of multi-chip modules (MCMs) including: laser processes for linking and cutting conductors; an interconnect net routing tool; and MCM assembly, test, and electrical characterization methods. Each component technology was successfully demonstrated through independent tests. The first integrated demonstration of these technologies is the customization of a three-chip MCM centered around a Motorola 88100-based chip set.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125588553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A multiprocessor architecture for circuit simulation 用于电路仿真的多处理器体系结构
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139987
J. Trotter, P. Agrawal
{"title":"A multiprocessor architecture for circuit simulation","authors":"J. Trotter, P. Agrawal","doi":"10.1109/ICCD.1991.139987","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139987","url":null,"abstract":"Circuit simulation uses a substantial amount of computation time to simulate a large circuit. A multiprocessor architecture can provide a cost effective way of speeding up the inner loop of the algorithm. A parallel processing architecture for circuit simulation algorithms that is designed as an accelerator system for workstations is presented. The architecture allows the inner loop of the circuit simulation algorithm, assembling the equations that describe the circuit and solving them, to be executed at high speed. It solves the large sets of equations using LU decomposition, which is both accurate and robust. The way in which the algorithms are supported by the distributed memory architecture and how this is reflected in the architecture's implementation are discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127919114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design verification and reachability analysis using algebraic manipulation 使用代数操作进行设计验证和可达性分析
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139892
S. Devadas, K. Keutzer, A. Krishnakumar
{"title":"Design verification and reachability analysis using algebraic manipulation","authors":"S. Devadas, K. Keutzer, A. Krishnakumar","doi":"10.1109/ICCD.1991.139892","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139892","url":null,"abstract":"Design verification is the process of checking that the specification of a circuit satisfies certain correctness properties. Approaches to design verification have involved the use of temporal logic and model checking, as well as the use of higher-order logic and theorem proving. Current approaches suffer from either limited expressivity of the logic, the state explosion problem, or difficulty in automating the verification process. The primary source of the complexity explosion in automata theoretic or temporal logic approaches is the state space explosion due to the need to construct the state space of the system under analysis. Symbolic analysis techniques are used based on linear algebra, specifically matrix multiplication, to compactly represent the state space of circuits described by a behavioral or register-transfer-level specification and thereby avoid this state space explosion, for classes of circuits.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124636379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations 惠普低成本PA-RISC工作站的系统级ASIC设计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139863
Leith Johnson, R. Horning, L. Thayer, Daniel Li, R. Snyder
{"title":"System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations","authors":"Leith Johnson, R. Horning, L. Thayer, Daniel Li, R. Snyder","doi":"10.1109/ICCD.1991.139863","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139863","url":null,"abstract":"The system architecture of a low cost PA-RISC workstation is described. This architecture is implemented in Hewlett-Packard's 9000 series 700 workstations. High performance and low cost are achieved through careful system partitioning and appropriate application of integration. The system design involved the development of four ASICs: a memory I/O system controller, a mixing buffer chip, a DRAM address decoder/buffer chip, and a controller for the built-in I/O functions. The system architecture is optimized to maximize performance for workstation workloads which include an emphasis on raw CPU performance, graphics, and I/O throughput.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121703783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Syndrome-based functional delay fault location in linear digital data-flow graphs 线性数字数据流图中基于证候的功能延迟故障定位
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139883
A. Chatterjee, M. d'Abreu
{"title":"Syndrome-based functional delay fault location in linear digital data-flow graphs","authors":"A. Chatterjee, M. d'Abreu","doi":"10.1109/ICCD.1991.139883","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139883","url":null,"abstract":"A novel approach to fault location in linear digital data flow graphs is presented. The fault location scheme is simple and depends on the linearity property of these data flow graphs. Identification and replacement of the failed component allows operation of the circuit at the desired clock speed. It is shown how timing problems identified during speed testing of a class of circuits widely used in digital signal processing and control can be isolated to individual or sets of circuit components.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126268561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Interlock schemes for micropipelines: application to a self-timed rebound sorter 微管道联锁方案:在自定时回弹分选机上的应用
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139927
S. Karthik, Indira de Souza, J. T. Rahmeh, J. Abraham
{"title":"Interlock schemes for micropipelines: application to a self-timed rebound sorter","authors":"S. Karthik, Indira de Souza, J. T. Rahmeh, J. Abraham","doi":"10.1109/ICCD.1991.139927","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139927","url":null,"abstract":"Event controlled pipelines (micropipelines) have several advantages over clocked pipelines as they offer modularity and speed independence. The concept of micropipelines can be easily applied to any linear pipeline. In practice, most pipelines include feedback loops and, therefore, are not as easy to control as linear pipelines. A novel interlocking scheme to solve the control flow problem is proposed. As an application, the design of a self-timed rebound sorter is considered where interlocking schemes are required to ensure proper operation of the pipeline. Similar interlocking schemes can be used for other pipelines with feedback.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Critical net routing 关键网络路由
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139875
J. Cohoon, L. J. Randall
{"title":"Critical net routing","authors":"J. Cohoon, L. J. Randall","doi":"10.1109/ICCD.1991.139875","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139875","url":null,"abstract":"A critical net has been routed traditionally by interconnecting its terminals with a minimum length rectilinear Steiner tree (MRST). A novel interconnection form, the maximum performance tree (MPT), that better approximates an interconnection with optimal circuit performance is proposed. In addition, a heuristic approach is presented that quickly generates MPTs, and the quality of these trees is compared with MRSTs for several net instances.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130563300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A genetic algorithm for global improvement of macrocell layouts 宏细胞布局全局改进的遗传算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139905
Klaus Glasmacher, A. Hess, G. Zimmermann
{"title":"A genetic algorithm for global improvement of macrocell layouts","authors":"Klaus Glasmacher, A. Hess, G. Zimmermann","doi":"10.1109/ICCD.1991.139905","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139905","url":null,"abstract":"The result of many floorplanning algorithms is a placement of macrocells. A novel technique for the improvement of a given placement is presented which is based on the optimization of the channel densities by refining the cell positions. The authors introduce a distance function for each channel representing the channel width. This width can be altered by shifting adjacent cells along each other by an offset. They present an optimization to find offsets for adjacent cells which lead to a minimal area demand of the total layout. The method is based on a genetic algorithm, an iterative improvement procedure. Results are presented.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"122 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131746378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Parallel event-driven waveform relaxation 并行事件驱动的波形松弛
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139854
Yen-Cheng Wen, K. Gallivan, R. Saleh
{"title":"Parallel event-driven waveform relaxation","authors":"Yen-Cheng Wen, K. Gallivan, R. Saleh","doi":"10.1109/ICCD.1991.139854","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139854","url":null,"abstract":"The implementation of asynchronous waveform relaxation on parallel processors is discussed. Three different approaches, all based on event-driven scheduling techniques, are compared to the standard data-flow scheme. Issues involving the use of priority queues and preemptive scheduling are described. Circuit examples are used to demonstrate that good speedup can be achieved by using the event-driven method. The results indicate that the combination of data-flow and event-driven scheduling, together with a suitable preemptive scheme, provides a speed improvement of 1.5 to 2.5 over standard data-flow scheduling on eight processors.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115210589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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